360×360-element very-high-frame-rate burst image sensor

Abstract

A 360x360-element very high frame rate (VHFR) burst image sensor captures images at maximum frame rate up to IO6 frame/s. This is accomplished by continuously storing the last 30 image frames a t the pixel locations. The 360x360 VHFR imager having a 2x2cm2 chip is designed in the form of 4 quadrants each with 180x180 pixels. Each pixel occupies 50x50pn2 and consists of a 337pm2 photodetector with a fill factor of 13.5% and a 3-phase 30stage (5x6) series-parallel type buried-channel CCD (BCCD) register for continuously storing the Past 30 detected image frames. The chip uses 1.5pm design rules and 1.5x3pm2 minimum-size BCCD storage elements.The architecture of the VHFR imager is illustrated in Figure 1 for an array of 2x2 pixels. Each pixel consists of a photodiode with charge-collecting well under the G, gate, a blooming barrier gate G,, a drain D, and the gate G, separating the charge collecting well from the 5-stage serial ( S ) register. The drain D is used for control of blooming during the optical (frame) integration time and for dumping the excess charge signals (excess frames) from the S register. However, the drain D could also facilitate the operation with subframe optical integration time. The 5-stage serial register coupled to a 5x5-stage parallel (P) register forms a 30-frame CCD storage at each pixel location. A block diagram of the 360x360 VHFR imager is shown in Figure 2. T h i s imager is organized into 4 quadrants to reduce transfer losses and to improve processing yield of usable quadrants. Note that all 360x360 photodetectors, PDs, have the same spacing, while the shape of the CCD pixel storage is different for upper and lower quadrants.During the image acquisition cycle, the charge signal detected by the photodetector, PD, is transferred in series into the serial BCCD register of the pixel for detection of the successive frames. After the detection of 5 frames, the detected charge signals are transferred in parallel from the S register to the P register, providing a storage for the last 30 detected image frames. The continuous storage of the last 30 frames is obtained by preceding the loading of the S register from the photodetector by a parallel transfer into the S register of the charge signals from the last row of the P register of the pixel above. This last row of 5 charge signals a t each pixel location is transferred to the dumping drain D while a new row of 5 charge signals corresponding to the next 5 frames i s transferred from the photodetector into the S register. The readout of the last detected 30 frames can be initiated aRer the loading of the S register is completed. This can be at the end of any pixel row-time. At this time, all of the BCCD storage registers of each quadrant are converted (under control of the BCCD clocks) into a single large frame-transfer type CCD readout of 180x(5+1) rows and 180x6 columns. For the 3-phase BCCD design, this charge readout involves up to 180x6~3 = 3,240 transfers in vertical direction by the parallel registers and up to 180x(5+1)x3 = 3,240 tra...

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