32nm overlay improvement capabilities

Eichelberger, Brad; Huang, Chung‐Che; O'Brien, Kelly; Tien, David; Tsai, Frank C.; Minvielle, Anna Maria; Singh, Lovejeet; Schefske, Jeffrey

doi:10.1117/12.773014

Cited by 8 publications

(8 citation statements)

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“…Kahng et al [15] have conducted field solver analysis to generate additional interconnect matching rules to help reduce design pessimism. Eichelberger et al [16] conduct variance analysis with respect to wafer exposure and develop higher-order models.…”

Section: Previous Workmentioning

confidence: 99%

ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration

Kahng¹,

Li²,

Peh³

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

549

338

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Double patterning lithography seems to be a prominent choice for 32nm and 22nm technologies. Double patterning lithography techniques require additional masks for a single interconnect layer. Consequently, mask shift-induced overlay errors introduce additional variability into interconnect coupling capacitances. An important open question is whether overlay-induced performance impacts are more significant than performance variations caused by variability in interconnects. We provide TCAD as well as chip-level analyses to determine whether overlay error should receive more attention than interconnect variations during interconnect manufacturing. We develop conclusions to help determine which component should be given more importance in specific double patterning process variants.

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Section: Previous Workmentioning

confidence: 99%

ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration

Kahng¹,

Li²,

Peh³

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

549

338

View full text Add to dashboard Cite

show abstract

“…On the other extreme, if overlay is completely random within-die variation, then POS of the die is p n , where n is the total number of critical spots in the design. Reality is closer to the former situation (since field and wafer level components dominate intra-field components [30]), which is our assumption in this paper.…”

Section: Manufacturabilitymentioning

confidence: 55%

DRE: A Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies

Ghaida

Gupta

2012

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Design rules have been the primary contract between technology developers and designers and are likely to remain so to preserve abstractions and productivity. While current approaches for defining design rules are largely unsystematic and empirical in nature, this paper offers a novel framework for early and systematic evaluation of design rules and layout styles in terms of major layout characteristics of area, manufacturability, and variability. The framework essentially creates a virtual standard-cell library and performs the evaluation based on the virtual layouts. Due to the focus on the exploration of rules at an early stage of technology development, we use first order models of variability and manufacturability (instead of relying on accurate simulation) and layout topology/congestion-based area estimates (instead of explicit and slow layout generation). Such a framework can be used to co-evaluate and co-optimize design rules, patterning technologies, layout methodologies, and library architectures.

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Section: Runtime and Validation Of Area Estimationmentioning

confidence: 55%

A framework for early and systematic evaluation of design rules

Ghaida

Gupta

2009

Proceedings of the 2009 International Conference on Computer-Aided Design

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Abstract-Design rules have been the primary contract between technology and design and are likely to remain so to preserve abstractions and productivity. While current approaches for defining design rules are largely unsystematic and empirical in nature, this paper offers a novel framework for early and systematic evaluation of design rules and layout styles in terms of major layout characteristics of area, manufacturability, and variability. Due to the focus on co-exploration in early stages of technology development, we use first order models of variability and manufacturability (instead of relying on accurate simulation) and layout topology/congestion-based area estimates (instead of explicit and slow layout generation). The framework is used to efficiently co-evaluate several debatable rules (evaluation for a 104-cell library takes 20 minutes). Results show that: a) diffusionrounding mainly from diffusion power-straps is a dominant source of variability, b) cell-area overhead of fixed gate-pitch implementation compared to 1D-poly implementation is tolerable (5%) given the improvement in variability, and c) 1D-poly restriction, which improves manufacturability and variability, has almost no area overhead compared to 2D-poly. In addition, we explore gate-spacing rules using our evaluation framework. This exploration yields almost identical values as those of a commercial 65nm process, which serves as a validation for our approach.

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32nm overlay improvement capabilities

Cited by 8 publications

References 0 publications

ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration

ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration

DRE: A Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies

A framework for early and systematic evaluation of design rules

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