32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays

Santiccioli, Alessio; Mercandelli, Mario; Dartizio, Simone M.; Tesolin, Francesco; Karman, Saleh; Shehata, Andrea Bahgat; Bertulessi, Luca; Buccoleri, Francesco; Avallone, Luca; Parisi, Angelo; Cherniak, Dmytro; Lacaita, A.L.; Kennedy, Michael Peter; Samori, Carlo; Levantino, Salvatore

doi:10.1109/isscc42613.2021.9365972

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Cited by 8 publications

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“…The self-biasing startup circuit was implemented in a 28-nm bulk CMOS technology and embedded in a 14-GHz oscillator with 31 coarse and 63 fine segmented digital capacitor banks and an analog tuning varactor, covering the 12.9-15.1-GHz frequency range [10], [11] [Fig. 3(a)].…”

Section: Implementation and Resultsmentioning

confidence: 99%

Self-Biasing Dynamic Startup Circuit for Current-Biased Class-C Oscillators

Parisi

Tesolin

Mercandelli

et al. 2021

IEEE Microw. Wireless Compon. Lett.

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This work presents a very compact self-biasing dynamic startup circuit for class-C voltage-controlled oscillators (VCOs). Using a referenceless nonlinear inverting stage, the solution has been implemented in a 28-nm CMOS technology 14-GHz oscillator, leading to a VCO startup time better than 20 ns, at par with the fastest startup circuits in literature, with an extremely compact area of 0.003 mm 2 .

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Section: Implementation and Resultsmentioning

confidence: 99%