2021 IEEE International Solid- State Circuits Conference (ISSCC) 2021
DOI: 10.1109/isscc42613.2021.9365949
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32.5 A 24GHz Self-Calibrated ADPLL-Based FMCW Synthesizer with 0.01% rms Frequency Error Under 3.2GHz Chirp Bandwidth and 320MHz/μs Slope

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Cited by 19 publications
(2 citation statements)
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“…For the FMCW radars, generating a fast and precise chirp is important since it can provide high spatial resolution [7,8,9,10,11,12,13,14,15]. A typical approach to achieve this is to employ a phase-locked loop (PLL) based frequency synthesizer [1,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29] with a wide loop bandwidth. However, increasing the loop bandwidth of a PLL can degrade phase noise and stability.…”
Section: Introductionmentioning
confidence: 99%
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“…For the FMCW radars, generating a fast and precise chirp is important since it can provide high spatial resolution [7,8,9,10,11,12,13,14,15]. A typical approach to achieve this is to employ a phase-locked loop (PLL) based frequency synthesizer [1,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29] with a wide loop bandwidth. However, increasing the loop bandwidth of a PLL can degrade phase noise and stability.…”
Section: Introductionmentioning
confidence: 99%
“…However, increasing the loop bandwidth of a PLL can degrade phase noise and stability. Another approach is to employ a PLL with a two-point modulation scheme to achieve a fast and accurate chirp regardless of its loop bandwidth [11,12,13,25,27,28]. However, it needs an additional calibration unit with a look-up table, which increases design complexity and needs updates of look-up table coefficients.…”
Section: Introductionmentioning
confidence: 99%