30Mrad(SiO2) radiation tolerant pixel front end for the BTEV experiment

Mekkaoui, A.; Hoff, J.

doi:10.1016/s0168-9002(01)00385-0

Cited by 26 publications

(10 citation statements)

References 4 publications

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“…The reason for this behaviour is that as the oxide thickness decreases, and in addition to thermal annealing, tunneling becomes possible and more effective at neutralizing radiation-induced charge. Deep submicron processes are, therefore, attractive for the design of ASIC's for experiments which involve pions, protons and other charged hadrons and neutrons [1][2][3]. However, using standard transistors and due to positive charge trapping that accumulates -------------------------------- of the device with external voltages applied is shown in Figure 1(b), where the origin of the axis of coordinates that we will consider in this analysis is taken at the centre of the inner diffusion and V GB , V DB and V SB are the gate, drain and source to bulk voltages, respectively.…”

Section: Introductionmentioning

confidence: 99%

A dc I–V model for short‐channel polygonal enclosed‐layout transistors

López

Hauer

Blanco-Filgueira

et al. 2008

Circuit Theory & Apps

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SUMMARYDespite the demonstrated radiation immunity of gate-enclosed layout transistors in deep submicron CMOS technologies, there is a significant lack of a thorough theoretical study addressing fundamental design issues on this kind of transistors. In this paper we propose a physical dc I -V model for short-channel polygonal-shape enclosed-layout transistors in both the linear and saturation regions of operation accounting for second-order effects such as depletion region non-uniformity, carrier velocity and channel length modulation. The impact of this layout style on the driving capability of the devices is also investigated. Experimental results based upon a fabricated NMOS test chip containing these devices in a standard 0.18 m CMOS technology process are presented. The comparison of the theoretical prediction with the experimental data show close agreement.

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Section: Introductionmentioning

confidence: 99%

A dc I–V model for short‐channel polygonal enclosed‐layout transistors

López

Hauer

Blanco-Filgueira

et al. 2008

Circuit Theory & Apps

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“…An ACcoupled amplifier further increases the analogue signal. Ultimately, a group of several discriminators form a flash ADC, providing over-threshold information and pulse-height digitization [7], [8].…”

Section: A Introductionmentioning

confidence: 99%

Radiation tolerance of prototype BTeV pixel detector readout chips

Chiodini

Appel

Cardoso

et al. 2002

IEEE Trans. Nucl. Sci.

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Abstract--High energy and nuclear physics experiments need tracking devices with increasing spatial precision and readout speed in the face of ever-higher track densities and increased radiation environments. The new generation of hybrid pixel detectors (arrays of silicon diodes bump bonded to arrays of front-end electronic cells) is the state of the art technology able to meet these challenges.We report on irradiation studies performed on BTeV pixel readout chip prototypes exposed to a 200 MeV proton beam at Indiana University Cyclotron Facility. Prototype pixel readout chip preFPIX2 has been developed at Fermilab for collider experiments and implemented in standard 0.25 micron CMOS technology following radiation tolerant design rules. The tests confirmed the radiation tolerance of the chip design to proton total dose up to 87 MRad. In addition, non destructive radiationinduced single event upsets have been observed in on-chip static registers and the single bit upset cross section has been extensively measured.

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“…In the following subsections we will concentrate on two readout chips for photon counting hybrid pixel detectors fabricated as a result of the efforts of the Medipix collaboration [44]. These are by no means the only devices of this type being developed in the world, and more information on other hybrid pixel detector systems can be found in e.g.…”

Section: Photon Counting Hybrid Pixel Detectorsmentioning

confidence: 99%

“…For example, the FPIX chip [44] to be used in the BTeV experiment in Fermilab uses a 3-bit flash ADC, and the readout chip for the pixel detector in the ATLAS Experiment [45] at CERN uses the Time Over Threshold technique [46] to determine the deposited energy. However, the application as well as the architecture of these chips are very different from the spectroscopic quantum imaging system described in this thesis.…”

Section: Pixel-level Analog-to-digital Convertersmentioning

confidence: 99%

Spectroscopic quantum imaging using pixel-level ADCS in semiconductor-based hyrid pixel detectors

Bello¹

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30Mrad(SiO2) radiation tolerant pixel front end for the BTEV experiment

Cited by 26 publications

References 4 publications

A dc I–V model for short‐channel polygonal enclosed‐layout transistors

A dc I–V model for short‐channel polygonal enclosed‐layout transistors

Radiation tolerance of prototype BTeV pixel detector readout chips

Spectroscopic quantum imaging using pixel-level ADCS in semiconductor-based hyrid pixel detectors

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