30.4 A 1Tb 3b/Cell 3D-Flash Memory in a 170+ Word-Line-Layer Technology

Tsutomu, Higuchi; Kodama, Tetsuya; Kato, Keizo; Fukuda, R.; Tokiwa, N.; Abe, Mitsuhiro; Takagiwa, Teruo; Shimizu, Yuki; Musha, Junji; Sakurai, Kazuo; Sato, Jumpei; Utsumi, Tetsuaki; Kazuhide, Yoneya; Suematsu, Yasuhiro; Hashimoto, Takahiro; Hioka, Takeshi; Yanagidaira, Kosuke; Kojima, Masayasu; Matsuno, Junya; Shiraishi, Kenji; Yamamoto, Kensuke; Hayashi, Shigenari; Hashiguchi, Tomoharu; Inuzuka, K.; Sugahara, Akio; Honma, Mareki; Tsunoda, Keiji; Yamamoto, Kazumasa; Sugimoto, Tsuneaki; Fujimura, Takuya; Kaneko, Mizuki; Date, Hiroki; Kobayashi, Osamu; Minamoto, Takatoshi; Tachibana, Ryoichi; Yamaguchi, Iwao; Lee, Juan; Ramachandra, Venky; Rajendra, Srinivas; Tang, Tianyu; Darne, Siddhesh; Lee, Jiwang; Li, Jason; Miwa, Takaki; Ryuji, Yamashita; Sugawara, Hiroshi; Ookuma, Naoki; Kano, Masahiro; Mizukoshi, Hiroyuki; Kuniyoshi, Yuki; Watanabe, Mitsuyuki; Akiyama, Kazuo; Mori, Hirotoshi; Arimizu, Akira; Katano, Y.; Ehama, Masakazu; Maejima, H.; Hosono, Koji; Yoshihara, Masahiro

doi:10.1109/isscc42613.2021.9366003

Cited by 16 publications

(4 citation statements)

References 4 publications

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“…4. The number of memory layers in 3D flash memory, such as BiCS FLASH™ , has increased from 96 layers to 170 layers over the past three years [5]. If the number of layers continues to increase at this rate, it is expected to reach around 1000 layers by 2030.…”

Section: A Memory Cell Technologymentioning

confidence: 99%

Flash Memory and Its Manufacturing Technology for Sustainable World

Ishimaru¹,

Fujiwara²,

Miyagawa³

et al. 2022

IEEE J. Electron Devices Soc.

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In today's data-driven society, memory is an unavoidable component. IoT and 5G are accelerating data generation exponentially, and the demands of high-capacity memory are increasing. Flash memory is a crucial infrastructure component and inevitable for Data Center. The advantages of a Solid-State Drive over a Hard Disk Drive are power consumption and volume per giga-byte. Low power consumption of storage devices, which are components of the data center itself, is critical in reducing power consumption, which has become a primary social concern. This paper describes current efforts and future trends in storage devices and their manufacturing technologies for realizing a sustainable society. New device structure which increases storage capacity with significant reduction of both materials and process steps, environmentally friendly and efficient manufacturing technologies and future technologies under consideration for even higher capacity will be shown. These technological innovations will make it possible to realize a society that enriches people's lives.

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Section: A Memory Cell Technologymentioning

confidence: 99%

Flash Memory and Its Manufacturing Technology for Sustainable World

Ishimaru¹,

Fujiwara²,

Miyagawa³

et al. 2022

IEEE J. Electron Devices Soc.

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“…Currently, cell under array (CuA) technology has secured space for more page buffer circuits and sense amplifiers, and so four-plane architecture with 16 KB is applied to most 3D NAND products [30,31,46,63], as shown in Figure 10a; this parallel technology contributes to higher read and program performance [70]. For further improvement, an independent multi-plane read operation is proposed, in which each group of two or four planes can perform read operations independently and asynchronously on any block/page address, thereby improving system level read and write performances [69,71,72], as shown in Figure 10b. In addition, J.-W. Park et al proposed a center-XDEC architecture and half-plane activation method [46].…”

Section: Improvement Of Read Performancementioning

confidence: 99%

A Review of Cell Operation Algorithm for 3D NAND Flash Memory

Park

Kim

2022

Applied Sciences

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The size of the memory market is expected to continue to expand due to the digital transformation triggered by the fourth industrial revolution. Among various types of memory, NAND flash memory has established itself as a major data storage medium based on excellent cell characteristics and manufacturability; as such, the demand for increasing the bit density and the performance has been rapidly increasing. In this paper, we will review the device operation algorithm and techniques to improve the cell characteristics and reliability in terms of optimization of individual program, read and erase operation, and system level performance.

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“…With the continuous development of smartphones, 5G, and data centers, the market demand for higher bit density has grown rapidly. The bit density is generally increased by stacking more layers in 3D NAND Flash [ 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 ]. However, stacking more layers makes integrated processes more complex, leading to worse wafer stress [ 9 , 10 , 11 ] and leakage caused by fluorine attack [ 12 ].…”

Section: Introductionmentioning

confidence: 99%

Activation Enhancement and Grain Size Improvement for Poly-Si Channel Vertical Transistor by Laser Thermal Annealing in 3D NAND Flash

et al. 2023

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The bit density is generally increased by stacking more layers in 3D NAND Flash. Lowering dopant activation of select transistors results from complex integrated processes. To improve channel dopant activation, the test structure of vertical channel transistors was used to investigate the influence of laser thermal annealing on dopant activation. The activation of channel doping by different thermal annealing methods was compared. The laser thermal annealing enhanced the channel activation rate by at least 23% more than limited temperature rapid thermal annealing. We then comprehensively explore the laser thermal annealing energy density on the influence of Poly-Si grain size and device performance. A clear correlation between grain size mean and grain size sigma, large grain size mean and sigma with large laser thermal annealing energy density. Large laser thermal annealing energy density leads to tightening threshold voltage and subthreshold swing distribution since Poly-Si grain size regrows for better grain size distribution with local grains optimization. As an enabler for next-generation technologies, laser thermal annealing will be highly applied in 3D NAND Flash for better device performance with stacking more layers, and opening new opportunities of novel 3D architectures in the semiconductor industry.

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30.4 A 1Tb 3b/Cell 3D-Flash Memory in a 170+ Word-Line-Layer Technology

Cited by 16 publications

References 4 publications

Flash Memory and Its Manufacturing Technology for Sustainable World

Flash Memory and Its Manufacturing Technology for Sustainable World

A Review of Cell Operation Algorithm for 3D NAND Flash Memory

Activation Enhancement and Grain Size Improvement for Poly-Si Channel Vertical Transistor by Laser Thermal Annealing in 3D NAND Flash

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