3-D Stacking of Ultrathin Chip Packages: An Innovative Packaging and Interconnection Technology

Priyabadini, Swarnakamal; Sterken, Tom; Hoorebeke, Luc Van; Vanfleteren, Jan

doi:10.1109/tcpmt.2012.2234830

Cited by 9 publications

(10 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The combination of both mechanical characteristics resulted in an A increased risk of die cracking during the lamination process. This effect has been reported in [9]. In order to control this risk of cracking, the topography can be reduced, thus creating a "Flat-UTCP" (Fig.…”

Section: Introductionmentioning

confidence: 76%

“…Priyabadini et al [9] characterized the stacking yield of the non-flat two-layered UTCP to be ƞ S ≈ 15% only, resulting in an overall yield ƞ eff of 7% following the simple equation on yield calculation (Eq. 1).…”

Section: B Utcp Stacking Processmentioning

confidence: 99%

“…1). As discussed in [9], topographical difference in the package (higher package thickness at the chip positions) adds the risk of die cracking during stacking process and this results in a very low ƞ s value for the conventional 2-PI layered UTCP technology. By adding a third polyimide layer, thus introducing the Flat-UTCP concept, this risk during the lamination process can be reduced and as a consequence the ƞ S value can be drastically increased.…”

Section: B Utcp Stacking Processmentioning

confidence: 99%

“…In the framework of the European Project TIPS, the process for 3D-stacking of Ultra-thin chip packages (UTCP) was developed to provide another way for fabricating devices with a minimal package volume. An overview of this technology resulting in the fabrication of a 300µm thick stack of 4 EEPROM memory dies was previously reported by Priyabadini et al [1,9]. This process is based on the first generation of UTCPs which consists of a chip embedding technology within two spin-on polyimide layers [2].…”

Section: Introductionmentioning

confidence: 99%

“…According to the stacking concept described in [9], the presence of one non-functional package in the stack makes the whole stack non-functional. To reduce the stacking yield loss due to this effect, a symmetry in package distribution is introduced.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

High-Yield Fabrication Process for 3D-Stacked Ultrathin Chip Packages Using Photo-Definable Polyimide and Symmetry in Packages

Priyabadini

Sterken

Cauwe

et al. 2014

IEEE Trans. Compon., Packag. Manufact. Technol.

Self Cite

View full text Add to dashboard Cite

Abstract-Getting output of multiple chips within the volume of a single chip is the driving force behind development of this novel 3D integration technology, which has a broad range of industrial and medical electronic applications. This goal is achieved in a two-step approach: at first thinned dies are embedded in a polyimide interposer with a fine-pitch metal fan-out resulting Ultra-Thin Chip Packages (UTCP), next these UTCPs are stacked by lamination.Step height at the chip edge of these UTCPs is the major reason of die cracking during the lamination. This paper contains an approach to solve this issue by introduction of an additional layer of interposer which makes it flat at the chip edge resulting in Flat-UTCP. In addition to that, randomness in non-functional package positions per panels reduces the overall yield of the whole process up to certain extend. A detailed analysis on these two issues to improve the process yield is given in this paper. 3D-stacked memory module composed of 4 EEPROM dies was processed and tested to demonstrate this new concept of enhanced fabrication yield.

show abstract

Section: Introductionmentioning

confidence: 76%

Section: B Utcp Stacking Processmentioning

confidence: 99%

Section: B Utcp Stacking Processmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

High-Yield Fabrication Process for 3D-Stacked Ultrathin Chip Packages Using Photo-Definable Polyimide and Symmetry in Packages

Priyabadini

Sterken

Cauwe

et al. 2014

IEEE Trans. Compon., Packag. Manufact. Technol.

Self Cite

View full text Add to dashboard Cite

show abstract

Highly Efficient Ultraviolet Third‐Harmonic Generation in an Isolated Thin Si Meta‐Structure

Deng,

Shi,

Zheng

et al. 2024

Advanced Science

View full text Add to dashboard Cite

Nonlinear nanophotonic devices have shown great potential for on‐chip information processing, quantum source, 3D microfabrication, greatly promoting the developments of integrated optics, quantum science, nanoscience and technologies, etc. To promote the applications of nonlinear nanodevices, improving the nonlinear efficiency, expanding the spectra region of nonlinear response and reducing device thickness are three key issues. Herein, this study focuses on the nonlinear effect of third‐harmonic generation (THG), and present a thin Si meta‐sructure to improve the THG efficiency in the ultraviolet (UV) region. The measured THG efficiency is up to 10−5 at an emission wavelength of 309 nm. Also, the THG nanosystem is only 100 nm in thickness, which is two–five times thinner than previous all‐dielectric nanosystems applied in THG studies. These findings not only present a powerful thin meta‐structure with highly efficient THG emission in UV region, but also provide a constructive avenue for further understanding the light–matter interactions at subwavelength scales, guiding the design and fabricating of advanced photonic devices in future.

show abstract

Mechanical Reliability Analysis of Ultra-Thin Chip-on-Foil Assemblies under Different Types of Recurrent Bending

Palavesam

Bonfert

Hell

et al. 2016

2016 IEEE 66th Electronic Components and Technology Conference (ECTC)

View full text Add to dashboard Cite

3-D Stacking of Ultrathin Chip Packages: An Innovative Packaging and Interconnection Technology

Cited by 9 publications

References 11 publications

High-Yield Fabrication Process for 3D-Stacked Ultrathin Chip Packages Using Photo-Definable Polyimide and Symmetry in Packages

High-Yield Fabrication Process for 3D-Stacked Ultrathin Chip Packages Using Photo-Definable Polyimide and Symmetry in Packages

Highly Efficient Ultraviolet Third‐Harmonic Generation in an Isolated Thin Si Meta‐Structure

Mechanical Reliability Analysis of Ultra-Thin Chip-on-Foil Assemblies under Different Types of Recurrent Bending

Contact Info

Product

Resources

About