3.5 A 16-to-40Gb/s quarter-rate NRZ/PAM4 dual-mode transmitter in 14nm CMOS

Abstract

Intel, Hillsboro, OREmerging standards in wireline communication are defining a path to data-rates of 40Gb/s and beyond. Most previous standards for these networking applications use NRZ signaling. However, practical signal integrity constraints have led to a renewed interest in also supporting PAM4 for some applications and loss profiles [1][2]. Recently, several transmitters have been reported that operate between 28 and 60Gb/s using NRZ or PAM4 modulation exclusively [2][3][4]. However, high-speed SerDes building blocks that support both a wide frequency range and multiple forms of modulation provide more compatibility between components and avoid the development of multiple IPs. In addition, these blocks must continue to scale into the next-generation of CMOS process technologies to lower the cost by reducing area and power consumption. This paper presents a dual-mode transmitter (TX) implemented in 14nm CMOS that supports both NRZ and PAM4 modulations and operates from 16 to 40Gb/s. The TX incorporates a 4-tap NRZ FIR filter that is reconfigurable to drive PAM4 levels, quarter-rate clocking with a high-bandwidth 4:1 serializer, a duty-cycle and quadrature-error correction circuit with statistical phase error detection, and compact, multi-layer T-coils for pad capacitance (C pad ) reduction.The TX block diagram is presented in Fig. 3.5.1. An on-chip pattern generator sends 8b parallel data to a mode selector through a 16:8 MUX. The data is further serialized for 4-tap FFE in NRZ mode or split into four 2b bundles (MSB and LSB) in PAM4 mode, and fed into the output stage that consists of 36 segments to cover equalization/modulation as well as PVT variation of the termination resistance. Each segment contains a retimer, an equalization (EQ) selector, a single-ended-to-differential (S2D) converter, a 4:1 serializer, a pre-driver, and a source-series terminated (SST) driver with a shared resistor. Figure 3.5.1 also illustrates the output stage segmentation for both NRZ and PAM4 modes. In NRZ mode, the segments are divided into three parts: cursor/1 st pre-cursor, cursor/2 nd pre-cursor, and cursor/post-cursor which contain ¼, ¼, and ½ of the total number of segments, respectively. The configurability of the NRZ TX taps supports a wide range of channel profiles while minimizing the number of segments. In PAM4 mode, the MSB is fed to ⅔ of the segments and the LSB is fed to ⅓ of the segments to generate four different voltage levels without providing equalization. The TX maintains quarter-rate clocking and operates at half the symbol rate of NRZ mode to maintain the same data and clock paths.While half-rate and quarter-rate architectures ideally consume the same CV 2 f power, a quarter-rate serialization scheme can be an attractive solution at very high data-rates because it relaxes the speed and timing requirements in the serializer. Figure 3.5.2 (a) shows the 4:1 serializer using back-to-back pass-gates. Compared to a 2:1 serializer, the 4:1 serializer relaxes the critical timing path by 2UI that is set by t ck-q ...

A 70 mW 25 Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset With 40 dB of Equalization in 65 nm CMOS Technology

“…Table III summarizes the measured performance of the TX described in this paper, in comparison to some recently published similar designs [5]- [8]. The one-channel power consumption of the TX working at 25 Gb/s is 21.8 mW, and the power efficiency is reduced by at least 17% compared with the other state-of-the-art designs.…”

“…To solve these power consumption problems, the quarter-rate TX architecture is proposed recently [8], [9], in which the highest-speed serialization is achieved by using the quarter-rate clocks exclusively. However, an extra delay-locked loop (DLL) [8] or a quadrature voltage-controlled oscillator (VCO) [9] is also required to generate at least 4 phases at the quarter-rate frequency. Moreover, the 4:1 MUX utilized in the aforementioned quarter-rate TX is far more difficult to design than the common 2:1 MUX.…”

A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration

“…Each transmission gate is enabled for 1-UI by ANDing two phases of the C8 clocks. While transmission gate structures have been used for 4:1 serializers [2,6], the use of eighth-rate clocks in this work enables a very low-latency 8:1 serializer. Serialized data is transmitted by a PFET CML driver with adjustable launch amplitude of between 100mVppd and 400mVppd [2].…”

Duty-cycle and phase spacing error correction circuit for high-speed serial link

“…The accuracy of the error detection and thus the error correction can be improved by asynchronous sampling which increases the effective sampling rate [9,10,11,12]. Because the frequency of an asynchronous sampling clock is different from that of a system clock, there must be an additional clock generation circuit [13,14,15,16]. This Letter describes a simple detection and correction schemes for duty cycle and phase spacing error for a 12-Gbps serial link transceiver.…”