3.3 A 14nm 1GHz FPGA with 2.5D transceiver integration

Greenhill, D.; Ho, Ron; Lewis, David; Schmit, Herman; Chan, Kok Hong; Andy, Tong; Atsatt, Sean; How, Dana; Peter, McElheny; Keith, Duwel; Jeffrey, Schulz; Darren, Faulkner; Iyer, G. Y. N.; Chen, George; Phoon, Hee Kong; Lim, Han Wooi; Koay, W.Y.; Garibay, Ty

doi:10.1109/isscc.2017.7870257

Cited by 41 publications

(5 citation statements)

References 3 publications

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“…Fig. 1 illustrates an example of advanced 2.5D package using multi-chiplet architecture [7]. In the figure, chiplets with various functions are placed on a silicon interposer using microbumps.…”

Section: Silicon Interposermentioning

confidence: 99%

Scene-aware Learning Network for Radar Object Detection

Zheng

Yue

Keutzer

et al. 2021

Proceedings of the 2021 International Conference on Multimedia Retrieval

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Object detection is essential to safe autonomous or assisted driving. Previous works usually utilize RGB images or LiDAR point clouds to identify and localize multiple objects in self-driving. However, cameras tend to fail in bad driving conditions, e.g. bad weather or weak lighting, while LiDAR scanners are too expensive to get widely deployed in commercial applications. Radar has been drawing more and more attention due to its robustness and low cost. In this paper, we propose a scene-aware radar learning framework for accurate and robust object detection. First, the learning framework contains branches conditioning on the scene category of the radar sequence; with each branch optimized for a specific type of scene. Second, three different 3D autoencoder-based architectures are proposed for radar object detection and ensemble learning is performed over the different architectures to further boost the final performance. Third, we propose novel scene-aware sequence mix augmentation (SceneMix) and scene-specific post-processing to generate more robust detection results. In the ROD2021 Challenge, we achieved a final result of average precision of 75.0% and an average recall of 81.0%. Moreover, in the parking lot scene, our framework ranks first with an average precision of 97.8% and an average recall of 98.6%, which demonstrates the effectiveness of our framework. CCS CONCEPTS• Computing methodologies → Object detection; Scene understanding; Neural networks.

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Section: Silicon Interposermentioning

confidence: 99%

Scene-aware Learning Network for Radar Object Detection

Zheng

Yue

Keutzer

et al. 2021

Proceedings of the 2021 International Conference on Multimedia Retrieval

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“…Though, the remainder of this work assumes a conservative projection of a 960MB L3 on an 826mm 2 die, which implies a maximum of 960MB L3 in a 3D COPA-GPU with single MSM die and 1920MB L3 in a 2.5D COPA-GPU with two MSM dies. High Bandwidth 2.5D and 3D Interconnects: High-speed links that enable 2.5D integration are rapidly maturing [16], [19], [43], [71]. Chen et al [16] recently demonstrated 20Gbps signaling rates across a 2.5mm silicon interposer layer at 0.3pJ/b, resulting in a ∼200GB/s/mm bandwidth density per layer, which can be further increased at shorter distances.…”

Section: E Copa-gpu Enabling Technologiesmentioning

confidence: 99%

GPU Domain Specialization via Composable On-Package Architecture

Fu¹,

Bolotin²,

Chatterjee³

et al. 2021

Preprint

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As GPUs scale their low precision matrix math throughput to boost deep learning (DL) performance, they upset the balance between math throughput and memory system capabilities. We demonstrate that converged GPU design trying to address diverging architectural requirements between FP32 (or larger) based HPC and FP16 (or smaller) based DL workloads results in sub-optimal configuration for either of the application domains. We argue that a Composable On-PAckage GPU (COPA-GPU) architecture to provide domain-specialized GPU products is the most practical solution to these diverging requirements. A COPA-GPU leverages multi-chip-module disaggregation to support maximal design reuse, along with memory system specialization per application domain. We show how a COPA-GPU enables DL-specialized products by modular augmentation of the baseline GPU architecture with up to 4× higher off-die bandwidth, 32× larger on-package cache, 2.3× higher DRAM bandwidth and capacity, while conveniently supporting scaled-down HPCoriented designs. This work explores the microarchitectural design necessary to enable composable GPUs and evaluates the benefits composability can provide to HPC, DL training, and DL inference. We show that when compared to a converged GPU design, a DL-optimized COPA-GPU featuring a combination of 16× larger cache capacity and 1.6× higher DRAM bandwidth scales per-GPU training and inference performance by 31% and 35% respectively and reduces the number of GPU instances by 50% in scale-out training scenarios.

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“…From the viewpoint of electron packaging applications, the design concept of chiplet arrangement was proposed to improve the yield and reduce product costs [27,28]. A dual-chiplet, interposer-based system-in-package architecture was demonstrated to establish a high-performance computing processor design, and the data rate of up to 8 Gb/s with relatively low power and area overhead was explored [29].…”

Section: Introductionmentioning

confidence: 99%

Layout Dependence Stress Investigation In Through Glass via Interposer Architecture Using Submodeling Simulation Technique and Factorial Design Approach

Wang¹,

Hsu²,

Liou³

et al. 2023

Preprint

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Multi-chiplet technique is expected to be a promising solution to achieve high-density system integration with low power consumption and high usage ratio. This technique can be integrated with glass interposer to accomplish a competitive low fabrication cost compared with the silicon-based interposer architecture. In this study, process-oriented stress simulation is performed by the element activation and de activation technique in finite element analysis architecture. Submodeling technique is also utilized to mainly conquer the scale mismatch and difficulty in mesh gridding design. It is used as well to analyze the thermomechanical responses of glass interposer with chiplet arrangement and capped epoxy molding compound (EMC) during curing. A three-factor, three-level full factorial design is applied using the analysis of variance method to explore the significance of various structural design parameters on stress generation. Analytic results reveal that the maximum first principal stresses of 130.75 and 17.18 MPa are introduced on the sidewall of Cu-filled via and the bottom of glass interposer, respectively. Moreover, the EMC thickness and through glass via pitch are the dominant factors in the adopted vehicle. They significantly influence the stress magnitude during heating and cooling.

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3.3 A 14nm 1GHz FPGA with 2.5D transceiver integration

Cited by 41 publications

References 3 publications

Scene-aware Learning Network for Radar Object Detection

Scene-aware Learning Network for Radar Object Detection

GPU Domain Specialization via Composable On-Package Architecture

Layout Dependence Stress Investigation In Through Glass via Interposer Architecture Using Submodeling Simulation Technique and Factorial Design Approach

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