2D modeling based comprehensive analysis of short channel effects in DMG strained VSTB FET

Silicon and Germanium Vertical Super-Thin Body (VSTB) FET: A Comparative Performance Overview Including Architectural Stress-Strain Impact

“…1 To address such issue, researchers suggested various non-classical FET structures such as silicon-on-insulator (SOI) FET, FinFET etc. [2][3][4][5][6][7][8][9][10][11][12][13][14][15] Moreover, multi-gate (double-gate/tri-gate) covering to channel is a widely used technique to enhance the gate controllability in many devices (planer FET/FinFET). 8,9,12 Although, these inventions have sufficiently suppressed SCEs in sub-micron devices, each of these structures has its own constraint.…”

“…If multiple gates cover a thin channel (in a 2D/3D device), then in on-state the carriers flowing through it feel strong multi-directional electric fields emanating from different gates; which results in increased carrier-carrier scattering and deteriorates drain current. [8][9][10][11][12][13] Thus the channel-thickness-downscaling in a multigate device is restricted by poor drive current issue. FinFET is an excellent breakthrough addressing different challenges obstruent to device miniaturization.…”

“…Such an absence of any support to the thin fin makes it more vulnerable to damage during the cleaning process by the sonication method. 9,11,[13][14][15][16] More importantly, as technological advancement focuses on increasing the aspect ratio (height-to-width) of fin, its mechanical stability is becoming poorer at lower technology nodes. 9,11,[13][14][15][16] This issue decreases the scalability of FinFETs.…”

“…9,11,[13][14][15][16] More importantly, as technological advancement focuses on increasing the aspect ratio (height-to-width) of fin, its mechanical stability is becoming poorer at lower technology nodes. 9,11,[13][14][15][16] This issue decreases the scalability of FinFETs. Thus to ensure an effective scaling and simultaneously to achieve high performance at lower manufacturing cost, further innovation in device structure is necessary.…”

“…Thus, at miniaturized scale, the fin in a VSTB FET is more robust to mechanical fragility than FinFET architecture. 9,11,[13][14][15][16] In addition, since a single gate controls the channel carrier kinetics, scattering reduces at thin channel devices, which increases drive current and makes the device more scalable. 9,11,[13][14][15][16] Besides, the fabrication of this new device is much simpler than SOI FETs.…”