2D analytical model for surface potential based electric field and impact of wok function in DMG SB MOSFET

Kumar, Prashanth; Bhowmick, Brinda

doi:10.1016/j.spmi.2017.06.001

Cited by 21 publications

(6 citation statements)

References 19 publications

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“…This level of loss is rather high and must be reduced for better reliability in operation. Hence, a more refined optimization or additional mitigation approaches, such as the introduction of an additional WF for one of the gate inputs [28], [29] to compensate or tune out such losses, may be necessary for more complex functions that require additional logic depth.…”

Section: Discussionmentioning

confidence: 99%

Ultracompact and Low-Power Logic Circuits via Workfunction Engineering

Canan

Kaya

Kodi

et al. 2019

IEEE J. Explor. Solid-State Comput. Devices Circuits

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An extensive analysis of sub-10-nm logic building blocks utilizing ultracompact logic gates based on recently proposed gate workfunction engineering (WFE) approach is provided. WFE sets the WF in the contacts as well as two independent gates of an ambipolar Schottky-barrier (SB) FinFET to alter the threshold of two channels, as a unique leverage to modify the logic functionality out of a single transistor. Thus, a single transistor (1T) CMOS pass-gate, 2T NAND and NOR gates as well as 3T or 4T XOR gates with substantial reduction in overall area (50%) and power (up to ×10) dissipation can be implemented. To harness this potential and illustrate the capabilities of these compact ambipolar transistors, novel logic building blocks, including 6T multiplexer, 8T full-adder, 4T latch, 6T D-type flip-flop, and 4T AND-OR-invert (AOI) gates, are developed. Besides the logic verification using 7-nm devices, the dynamic performance of the proposed logic circuits is also analyzed. The comparative simulation study shows that WFE in independent-gate SB-FinFETs can lead to absolutely minimalist CMOS logic blocks without significant degradation to overall power-delay product (PDP) performance. INDEX TERMS 3T-XOR, 4T AND-OR-invert (AOI), 6T 4-to-1 multiplexer (MUX), ambipolar, CMOS logic gates, nanotechnology, Schottky-barrier MOSFET, tunneling.

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Section: Discussionmentioning

confidence: 99%

Ultracompact and Low-Power Logic Circuits via Workfunction Engineering

Canan

Kaya

Kodi

et al. 2019

IEEE J. Explor. Solid-State Comput. Devices Circuits

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“…The surface potential ψ ( x , y ) in silicon film can be approximated by parabolic functions in y‐direction can be expressed as

ψ_{1} ((),, x, y) = ψ_{s 1} ((), x) + D_{11} ((), x) y + D_{12} ((), x) y^{2},

for 0 ≤ x ≤ L 1 , 0 ≤ y ≤ t si

ψ_{2} ((),, x, y) = ψ_{s 2} ((), x) + D_{21} ((), x) y + D_{22} ((), x) y^{2},

for L 2 ≤ x ≤ L 1 + L 2 , 0 ≤ y ≤ t si where the arbitrary coefficients D 11 ( x ), D 12 ( x ), D 21 ( x ), and D 22 ( x ) are functions of variable x . () can be solved by using the following boundary conditions The potential at the source/channel interface is

ψ_{1} ((),, 0, 0) = ψ_{S 1} ((), 0) = V_{italicbi, S / D} - normalΔ φ_{bS} .

The potential at the drain/channel interface is

ψ_{1} ((),, L_{1} + L_{2}, 0) = ψ_{2} ((), L_{1} + L_{2}) = V_{italicbi, S / D} - normalΔ φ_{bD} + V_{DS},

where Δ φ bS and Δ φ bD are SB lowering at the source and drain . V bi , S / D is the built‐in potential at the source/drain

V_{italicbi, S / D} = χ + \frac{E_{g}}{2} + φ_{F} - φ_{S / D},

…”

Section: Model Derivationmentioning

confidence: 99%

“…where Δφ bS and Δφ bD are SB lowering at the source and drain. 17,25 V bi, S/D is the built-in potential at the source/drain…”

Section: Model Derivationmentioning

confidence: 99%

“…The alternative method to enhance the I on current is to increase the pocket doping are applied in SB‐TFET . The SB‐MOSFET with a full‐depleted pocket doping in between the metal and lightly doped channel region is proposed to improve the tunneling of carrier is successfully fabricated . In addition, high‐k dielectric such as HfO 2 are used in SB‐MOSFET to decrease the equivalent oxide thickness and increase the electrical coupling between the Schottky tunnel junction and gate electrode, resulting in better performance of the SB‐MOSFET .…”

Section: Introductionmentioning

confidence: 99%

“…16 The SB-MOSFET with a full-depleted pocket doping in between the metal and lightly doped channel region is proposed to improve the tunneling of carrier is successfully fabricated. [17][18][19] In addition, high-k dielectric such as HfO 2 are used in SB-MOSFET to decrease the equivalent oxide thickness and increase the electrical coupling between the Schottky tunnel junction and gate electrode, resulting in better performance of the SB-MOSFET. 20 The SB-MOSFET with high-k gate dielectric suggests a required I on current and I off current, but the ambipolar current cannot be obstructed adequately.…”

Section: Introductionmentioning

confidence: 99%

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A physics‐based threshold voltage model for hetero‐dielectric dual material gate Schottky barrier MOSFET

Kumar

Bhowmick

2018

Int J Numerical Modelling

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This paper presents the analytical model of threshold voltage for hetero‐dielectric dual material gate Schottky barrier (SB) metal oxide semiconductor field effect transistor (MOSFET). The threshold voltage model is derived on the basis of the surface potential model. The threshold voltage is extracted using transconductance change method. The two‐dimensional surface potential, electric field, and threshold voltage model for the hetero‐dielectric dual material gate SB‐MOSFET are developed using 2‐D Poisson's equation, which satisfies the boundary conditions. Moreover, the model precisely depict the impact of hetero‐gate dielectric and gate oxide thickness on the surface potential, and threshold voltage of the hetero‐dielectric dual material gate SB and compared with single material gate SB‐MOSFET. Finally, a good agreement between the model results and numerical simulated results is achieved.

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