28nm high-K metal gate heterogeneous quad-core CPUs for high-performance and energy-efficient mobile application processor

Wang

Proceedings of the 19th International Conference on Architectural Support for Programming Languages and Operating Systems

2014

Mobile System-on-Chips (SoC) that incorporate heterogeneous coherence domains promise high energy efficiency to a wide range of mobile applications, yet are difficult to program. To exploit the architecture, a desirable, yet missing capability is to replicate operating system (OS) services over multiple coherence domains with minimum inter-domain communication. In designing such an OS, we set three goals: to ease application development, to simplify OS engineering, and to preserve the current OS performance. To this end, we identify a shared-most OS model for multiple coherence domains: creating per-domain instances of core OS services with no shared state, while enabling other extended OS services to share state across domains. To test the model, we build K2, a prototype OS on the TI OMAP4 SoC, by reusing most of the Linux 3.4 source. K2 presents a single system image to applications with its two kernels running on top of the two coherence domains of OMAP4. The two kernels have independent instances of core OS services, such as page allocator and interrupt management, as coordinated by K2; the two kernels share most extended OS services, such as device drivers, whose state is kept coherent transparently by K2. Despite platform constraints and unoptimized code, K2 improves energy efficiency for light OS workloads by 8x-10x, while incurring less than 6% performance overhead for a device driver shared between kernels. Our experiences with K2 show that the shared-most model is promising.

Section: Coherent Heterogeneous Socmentioning

confidence: 99%

K2

Wang

Proceedings of the 19th International Conference on Architectural Support for Programming Languages and Operating Systems

2014

21st IEEE Real-Time and Embedded Technology and Applications Symposium

“…Other designs aggressively power-gate cores, so that unused cores can be idled to further reduce power consumption [42]. Recent designs, such as the Exynos5 SoC (in the Samsung Galaxy line), support heterogeneous cores where different cores have different performance and energy tradeoffs [27,45].…”

Section: Introductionmentioning

confidence: 99%

POET: a portable approach to minimizing energy under soft real-time constraints

Imes

Kim

Maggio

et al. 2015

Embedded real-time systems must meet timing constraints while minimizing energy consumption. To this end, many energy optimizations are introduced for specific platforms or specific applications. These solutions are not portable, however, and when the application or the platform change, these solutions must be redesigned. Portable techniques are hard to develop due to the varying tradeoffs experienced with different application/platform configurations. This paper addresses the problem of finding and exploiting general tradeoffs, using control theory and mathematical optimization to achieve energy minimization under soft real-time application constraints. The paper presents POET, an open-source C library and runtime system that takes a specification of the platform resources and optimizes the application execution. We test POET's ability to portably deliver predictable timing and energy reduction on two embedded systems with different tradeoff spaces -the first with a mobile Intel Haswell processor, and the second with an ARM big.LITTLE System on Chip. POET achieves the desired latency goals with small error while consuming, on average, only 1.3% more energy than the dynamic optimal oracle on the Haswell and 2.9% more on the ARM. We believe this open-source, librarybased approach to resource management will simplify the process of writing portable, energy-efficient code for embedded systems.

IEIE Transactions on Smart Processing and Computing

“…Commercial application processor cores pursuing only performance maximization have lots of complex fill-ratesustaining structures (FRS) including register renaming, reorder buffers, and instruction fetch speculation units [1]. A deeply pipelined processor core focusing on throughput enhancement necessitates implementation of a powerhungry FRS to sustain the instruction fill rate in pipeline stages of the core.…”

Section: Introductionmentioning

confidence: 99%

80μW/MHz 0.68V Ultra Low-Power Variation-Tolerant Superscalar Dual-Core Application Processor

Kwon

Lee²,

Shin³

et al. 2015

Upcoming ground-breaking applications for always-on tiny interconnected devices steadily demand two-fold features of processor cores: aggressively low power consumption and enhanced performance. We propose implementation of a novel superscalar low-power processor core with a low supply voltage. The core implements intra-core low-power microarchitecture with minimal performance degradation in instruction fetch, branch prediction, scheduling, and execution units. The inter-core lockstep not only detects malfunctions during low-voltage operation but also carries out software-based recovery. The chip incorporates a pair of cores, high-speed memory, and peripheral interfaces to be implemented with a 65nm node. The processor core consumes only 24mW at 350MHz and 0.68V, resulting in power efficiency of 80 W/MHz. The operating frequency of the core reaches 850MHz at 1.2V.