26.6 A 5GS/S 150mW 10b SHA-less pipelined/SAR hybrid ADC in 28nm CMOS

Brandolini, M.; Shin, Young Jae; Raviprakash, K.; Wang, Tao; Wu, Rong; Geddada, Hemasundar Mohan; Ko, Yen-Jen; Ding, Yen; Huang, Chun‐Sheng; Shin, Wei-Ta; Hsieh, Ming-Hung; Chou, Wei-Te; Li, Tianwei; Shrivastava, Ayaskant; Chen, Yi‐Chun; Hung, Juo-Jung; Cusmai, G.; Wu, Jiangfeng; Zhang, Mo M.; Unruh, Greg; Venes, Ardie; Huang, Hung Sen; Chen, Chunying

doi:10.1109/isscc.2015.7063129

Cited by 20 publications

(2 citation statements)

References 3 publications

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“…The designers can obtain better performances of ADC than in a monolithic chip with the help of Hybrid ADCs [83][84][85][86][87][88][89][90]. Employing Hybrid structured ADC [91][92][93][94], different parameters of ADC such as sampling rate, scaling, resolution, calibration free and so on can be improved.…”

Section: Fig 6: Zoomed In View Of Adc Core [21]mentioning

confidence: 99%

Analog to Digital Converters (ADC): A Literature Review

Dalmia

Sinha

2020

E3S Web Conf.

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The signal processing is advancing day by day as its needs and in wireline/wireless communication technology from 2G to 4G cellular communication technology with CMOS scaling process. In this context the high-performance ADCs, analog to digital converters have snatched the attention in the field of digital signal processing. The primary emphasis is on low power approaches to circuits, algorithms and architectures that apply to wireless systems. Different techniques are used for reducing power consumption by using low power supply, reduced threshold voltage, scaling of transistors, etc. In this paper, we have discussed the different types and different techniques used for analog to digital conversion of signals considering several parameters.

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Section: Fig 6: Zoomed In View Of Adc Core [21]mentioning

confidence: 99%

Analog to Digital Converters (ADC): A Literature Review

Dalmia

Sinha

2020

E3S Web Conf.

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“…Based on high performance SAR ADC, time-interleaved SAR ADCs (TI SAR ADC) are superior in aspects of highly scalable and power efficiency to advanced CMOS technology. Several calibration techniques are provided in [23,24,25,26,27,28] to correct the non-ideal errors produced by channel mismatches in time-interleaved SAR ADC. For every type of SAR ADCs, linearity of sampling switch is the bottleneck for system linearity, the parasitic diodes of source/drain to substrate exist in the sampling switch.…”

Section: Introductionmentioning

confidence: 99%

A 12-bit 100-MS/s 83 dB SFDR SAR ADC with sampling switch linearity enhanced technique

Pu-Jie

et al. 2019

IEICE Electron. Express

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A 12-bit 100-MS/s 83 dB SFDR SAR ADC with sampling switch linearity enhanced technique is proposed. With the variation of input signals, the parasitic capacitance variation of sampling switch is reduced and the total parasitic capacitance is also depressed. Moreover, with substrate boost technique, the on-impedance of sampling switch would decrease. To demonstrate the proposed technique, a design of 12bit 100-MS/s SAR ADC is fabricated in 40-nm CMOS technology, consuming 2 mW from 1 V power supply with a SNDR >65 dB and SFDR >83 dB. The proposed ADC core occupies an active area of 0.02 mm 2 , and the corresponding FoM is 13.8 fJ/conversion-step with Nyquist frequency.

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Hybrid Data Converters

Doris

2017

Hybrid ADCs, Smart Sensors for the IoT, and Sub-1v &Amp; Advanced Node Analog Circuit Design

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26.6 A 5GS/S 150mW 10b SHA-less pipelined/SAR hybrid ADC in 28nm CMOS

Cited by 20 publications

References 3 publications

Analog to Digital Converters (ADC): A Literature Review

Analog to Digital Converters (ADC): A Literature Review

A 12-bit 100-MS/s 83 dB SFDR SAR ADC with sampling switch linearity enhanced technique

Hybrid Data Converters

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