25V sampling switch for power management data converters in 0.35&amp;#x00B5;m CMOS with DNMOS

Aksin, Devrim Yılmaz; Özkaya, İlter

doi:10.1109/esscirc.2009.5326015

Cited by 9 publications

(8 citation statements)

References 5 publications

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“…Due to the cross-coupled sampling scheme, M 1−4 can share one set of coupling capacitors. Compared to the HV switch proposed in [14], this design is 3× smaller, occupying only 0.01 mm 2 .…”

Section: B Hv Input Choppermentioning

confidence: 97%

A ±4-A High-Side Current Sensor With 0.9% Gain Error From −40 °C to 85 °C Using an Analog Temperature Compensation Technique

Huijsing

Makinwa

2018

IEEE J. Solid-State Circuits

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This paper presents a fully integrated shunt-based current sensor that supports a 25-V input common-mode range while operating from a single 1.5-V supply. It uses a highvoltage beyond-the-rails ADC to directly digitize the voltage across an on-chip shunt resistor. To compensate for the shunt's large temperature coefficient of resistance (∼0.335%/°C), the ADC employs a proportional-to-absolute-temperature voltage reference. This analog compensation scheme obviates the need for the explicit temperature sensor and calibration logic required by digital compensation schemes. The sensor achieves 1.5-μV rms noise over a 2-ms conversion time while drawing only 10.9 μA from a 1.5-V supply. Over a ±4-A range, and after a one-point trim, the sensor exhibits a 0.9% (maximum) gain error from −40°C to 85°C and a 0.05% gain error at room temperature.

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Section: B Hv Input Choppermentioning

confidence: 97%

A ±4-A High-Side Current Sensor With 0.9% Gain Error From −40 °C to 85 °C Using an Analog Temperature Compensation Technique

Huijsing

Makinwa

2018

IEEE J. Solid-State Circuits

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“…As the stacked battery channels increase, higher voltage devices are utilized to design the switches, however, it occupies more area than low voltage (LV) device does, besides, bigger parasitic parameters reduce the speed. Many papers focus on low area switches [2,3,4,5,6,7,8], but they just focus on the area and speed of switches, and taking limited improvement. To save the whole chip area and speed, we propose a novel full differential leapfrog sampling.…”

Section: Introductionmentioning

confidence: 99%

An area-efficient and high speed multiplexer for battery monitor system

Zhang

Yang

Chai

2016

IEICE Electron. Express

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This paper presents a new area-efficient and fast sampling multiplexer for battery monitor system. This multiplexer structure introduces a full differential leapfrog sampling scheme which leads to half of occupied area, less sampling time and higher common mode rejection rate (CMRR) than the traditional one. This kind of multiplexer structure was introduced in a 12-ch battery monitor IC which fabricated with 60 V BCD process. The measurement result shows that the presented multiplexer achieves a channel mismatch error up to 1.2 mV (Typical) while the battery monitor IC works in 400 ns sampling time.

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mentioning

confidence: 99%

“…Due to the cross-coupled sampling scheme, the 4 switches of the HV chopper can share one set of coupling capacitors. Compared to other HV switches [5], this capacitively coupled HV chopper is 3× smaller, occupying only 0.012mm 2 .Since the coupled clock signals are superimposed on V min, their amplitude determines the maximum DVR of the chopper switches. This is because the switches can only be turned on if the amplitude of the differential input signal is less than their overdrive voltage.…”

mentioning

confidence: 99%

5.2 A 110dB SNR ADC with ±30V input common-mode range and 8μV Offset for current sensing applications

Gönen

Fan³

et al. 2015

2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers

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This paper presents a high-resolution 110dB SNR ΔΣ ADC that achieves a ±30V input common-mode voltage range (CMVR) while powered from a single 5V supply. This beyond-the-rails capability is obtained by employing a capacitively coupled high-voltage (HV) chopper at the input of a switched-capacitor (SC) ΔΣ ADC. Furthermore, the use of correlated double sampling and system-level chopping results in a maximum offset of 8μV over the full CMVR. In contrast to a recent HV ADC [1], the ADC exhibits 30dB more resolution, while its CMVR extends below the negative rail.The ADC is intended for current monitoring applications, in which a small voltage drop across a shunt resistor must be digitized. In battery monitoring applications, or when inductive loads are involved, the differential voltage across the shunt will often be accompanied by beyond-the-rails common-mode (CM) voltages. Conventionally, current monitoring systems consist of a precision current sensing amplifier (CSA) with a wide CMVR, whose output is then digitized by an ADC [2]. The CSA thus isolates the ADC from large CM voltages, while its gain relaxes the ADC noise requirements. Since the presented ADC itself has beyond-the-rails CM capability together with high resolution, low offset and high gain accuracy, it obviates the need for the CSA, thus reducing the power consumption and the silicon area of the resulting current monitoring system. Figure 5.2.1 shows the block diagram of the ADC. It consists of a single-loop single-bit 3 rd -order SC ΔΣ ADC with a feed-forward architecture based on three OTAs and a SC summing network. An inner set of HV choppers, CH in , together with switches Φ1 and Φ2, implement a correlated double sampling (CDS) scheme that mitigates the effect of offset and 1/f noise of the 1 st OTA. Further offset reduction is obtained with the help of an outer set of HV choppers, CH sys , which, together with a digital chopper at the output of the modulator, implement a system-level chopping scheme. During Φ1, the input signal, V in , and the OTA offset are sampled on the 5pF input capacitors, C s . During Φ2, the HV chopper, CH in , reverses the input and thus transfers a charge packet proportional to 2•C s •V in to the integration capacitors, C int . This cross-coupled sampling scheme [3] ensures that the only components exposed to the input CM voltage are the capacitors C s and two capacitively coupled HV choppers. The input capacitors are implemented as HV fringe capacitors with a breakdown voltage of 80V. The feedback capacitors are also implemented with the same type of capacitors, to ensure good matching and hence, good gain accuracy.Figure 5.2.2 shows the schematic of the capacitively-coupled HV chopper, which consists of 4 sampling switches MN 1-4 , one dynamic latch MN 5,6 , three coupling capacitors C 1-3 and a minimum selector MN S1-2 . All the transistors are 5V NMOS devices located in an isolated HV N-Epi pocket (Fig. 5.2.2). The N-Epi pocket is capable of floating up to 65V with regard to the grounded P-Substrate, while the local...

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25V sampling switch for power management data converters in 0.35µm CMOS with DNMOS

Cited by 9 publications

References 5 publications

A ±4-A High-Side Current Sensor With 0.9% Gain Error From −40 °C to 85 °C Using an Analog Temperature Compensation Technique

A ±4-A High-Side Current Sensor With 0.9% Gain Error From −40 °C to 85 °C Using an Analog Temperature Compensation Technique

An area-efficient and high speed multiplexer for battery monitor system

5.2 A 110dB SNR ADC with ±30V input common-mode range and 8μV Offset for current sensing applications

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