High performance tunnel field-effect transistor by gate and source engineering

Huang, Ru; Huang, Qianqian; Chen, Shaowen; Wu, Chunlei; Wang, Jiaxin; An, Xia; Wang, Yangyuan

doi:10.1088/0957-4484/25/50/505201

Cited by 18 publications

(10 citation statements)

References 28 publications

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“…With this layer, the effective length of tunneling path is reduced and results to an obvious tunneling rate enhancement. Moreover, TFETs with improved gate structure are studied by many research groups [12][13][14][15][16][17][18][19][20]. The concept of line tunneling is introduced in L-TFET [17][18][19].…”

Section: Introductionmentioning

confidence: 99%

A Novel Dopingless Fin-Shaped SiGe Channel TFET with Improved Performance

et al. 2020

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In this paper, a dopingless fin-shaped SiGe channel TFET (DF-TFET) is proposed and studied. To form a high-efficiency dopingless line tunneling junction, a fin-shaped SiGe channel and a gate/source overlap are induced. Through these methods, the DF-TFET with high on-state current, switching ratio of 12 orders of magnitude and no obvious ambipolar effect can be obtained. High κ material stack gate dielectric is induced to improve the off-state leakage, interface characteristics and the reliability of DF-TFET. Moreover, by using the dopingless channel and fin structure, the difficulties of doping process and asymmetric gate overlap formation can be resolved. As a result, the structure of DF-TFET can possess good manufacture applicability and remarkably reduce footprint. The physical mechanism of device and the effect of parameters on performance are studied in this work. Finally, on-state current (ION) of 58.8 μA/μm, minimum subthreshold swing of 2.8 mV/dec (SSmin), average subthreshold swing (SSavg) of 18.2 mV/dec can be obtained. With improved capacitance characteristics, cutoff frequency of 5.04 GHz and gain bandwidth product of 1.29 GHz can be obtained. With improved performance and robustness, DF-TFET can be a very attractive candidate for ultra-low-power applications.

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Section: Introductionmentioning

confidence: 99%

A Novel Dopingless Fin-Shaped SiGe Channel TFET with Improved Performance

et al. 2020

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“…The buried oxide layer (BOX) which for SOI is SiO2 the dielectric layer that separates the top device layer and the handler wafer. These substrates are used for opto-electronic applications as well [2,3]. Recently high sensitivity broad band opticaldetectors (UV to NIR) have been produced by fabricating micro and sub-micron width arrays on SOI wafers [4,5].…”

Section: Introductionmentioning

confidence: 99%

Fabrication of Germanium-on-insulator in a Ge wafer with a crystalline Ge top layer and buried GeO2 layer by oxygen ion implantation

Aggarwal

Ghatak

Kanjilal

et al. 2020

Materials Science and Engineering: B

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The paper reports fabrication of Germanium-on-Insulator (GeOI) wafer by Oxygen ion implantation of an undoped single crystalline Ge wafer of orientation (100). O + ions of energy 200 keV were implanted to a fluence of 1.9 x 10 18 ions-cm-2 and the implanted wafer was subjected to Rapid Thermal Annealing to 650 0 C. The resulting wafer has a topcrystalline Ge layer of ~ 220 nm thickness and Buried Oxide layer (BOX) layer of good quality crystalline GeO2 with thickness around 0.75µm. The crystalline GeO2 layer has hexagonal crystal structure with lattice constants close to the standard values. Raman Spectroscopy, cross-sectional HRTEM with SAED and EDS established that the top Ge layer was recrystallized during annealing with faceted crystallites. The top layer (resistivity ≈32 ohm.cm) has a small tensile strain of around +0.4% and has estimated dislocation density of 2.7x10 7 cm-2. The thickness, crystallinity and electrical characteristics of the top layer and thequality of the BOX layer of GeO2 are such that it can be utilized for device fabrication.

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“…On the other hand, the fundamental theoretical limit of the subthreshold swing (SS), which is about 60 mV/dec at room temperature for conventional MOSFETs, does not permit further decrease of the leakage current in these devices. Therefore alternative device structures and materials are proposed to overcome these problems [1][2][3][4][5][6][7]. They could offer a subthreshold swing (SS) smaller than 60 mV/dec [2].…”

Section: Introductionmentioning

confidence: 99%

First Principles Study of the Ambipolarity in a Germanene Nanoribbon Tunneling Field Effect Transistor

Samipour

Dideban

Heidari

2019

ECS J. Solid State Sci. Technol.

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In this article, the effects of hetero-dielectric gate material and gate-drain underlap on the ambipolar and ON-state current of a germanene nanoribbon (GeNR) tunneling field-effect transistors (TFETs) is examined. The simulations are performed using the combination of density functional theory (DFT) and nonequilibrium Green's function (NEGF) formalis m. It was observed that using high-k dielectric gate material increases the ON-state current while the combination of hetero-dielectric gate material and gate-drain underlap suppresses the ambipolar current and improves the ON-state current. In addition, the effect of various hetero-junctions in the source region on the performance of GeNR-TFET was investigated. Due to the dependency between the width and energy bandgap in GeNR, utilizing a small bandgap in the source improves ON-state current and its ambipolar behavior.

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High performance tunnel field-effect transistor by gate and source engineering

Cited by 18 publications

References 28 publications

A Novel Dopingless Fin-Shaped SiGe Channel TFET with Improved Performance

A Novel Dopingless Fin-Shaped SiGe Channel TFET with Improved Performance

Fabrication of Germanium-on-insulator in a Ge wafer with a crystalline Ge top layer and buried GeO2 layer by oxygen ion implantation

First Principles Study of the Ambipolarity in a Germanene Nanoribbon Tunneling Field Effect Transistor

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