Design and fabrication of a perpendicular magnetic tunnel junction based nonvolatile programmable switch achieving 40% less area using shared-control transistor structure

Suzuki, Daisuke; Natsui, Masanori; Mochizuki, Ayako; Miura, Shigeto; Honjo, Haruo; Kinoshita, Keizo; Fukami, Shunsuke; Sato, Hideo; Ikeda, Shoji; Endoh, Tetsuo; Ohno, Hideo; Hanyu, Takahiro

doi:10.1063/1.4868332

Cited by 11 publications

(5 citation statements)

References 17 publications

(19 reference statements)

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“…Figure 5 shows the block diagram of the address generator. This is composed of the Kbit nonvolatile latch 37) for storing the length of the maximum number of the address (A MAX ), which corresponds the length of the shift register; the Kbit nonvolatile flip-flop (FF) 38) for storing the current address (A IN ), and the K bit incrementer. To implement shift registers of various length, several address generators are used.…”

Section: Making Of Shift Controllermentioning

confidence: 99%

Design of a cost-efficient controller for realizing a data-shift-minimized nonvolatile field-programmable gate array

Suzuki

Hanyu

2020

Jpn. J. Appl. Phys.

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Data shifting occupies an important function as a lookup table (LUT) circuit in a field-programmable gate array (FPGA), while its write energy is critical in magnetic tunnel junction (MTJ)-based nonvolatile FPGAs (NV-FPGAs). Minimizing data shifting by only permuting the order of the output data stream from the stored data in an LUT is an energy-efficient approach to solving the above problem. However, a concrete and energy-efficient controller design has not been discussed. In this paper, we propose a cost-efficient controller for realizing data-shift-minimized MTJ-based NV-FPGA. The hardware overhead in the proposed controller is significantly reduced by sharing the common functionality. In fact, the hardware overhead of the proposed controller is 68% smaller that of without hardware sharing. It is also demonstrated that the power consumption of the 512 bit shift register using MTJ-based LUT circuits with proposed controller is 88% smaller than that of SRAM-based one.

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Section: Making Of Shift Controllermentioning

confidence: 99%

Design of a cost-efficient controller for realizing a data-shift-minimized nonvolatile field-programmable gate array

Suzuki

Hanyu

2020

Jpn. J. Appl. Phys.

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“…28,29) The asymmetric characteristics have not been clearly defined theoretically, and we assumed the ratio between η AP and η P to be as described by Eq. ( 6), where 0.6 is obtained for our 17) simulation by fitting the results obtained using the P-MTJ sample introduced by Suzuki et al 30)…”

Section: Write Current Modelingmentioning

confidence: 99%

“…On the basis of Eqs. ( 1)-( 8) above, we performed fitting simulations based on P-MTJ introduced by Suzuki et al in 2014, which shows critical current values of 50 µA for P to AP and 80 µA for AP to P. 30) By considering the sample, we performed simulation assuming that I CPtoAP is 50 µA for MTJ with a cell diameter of 75 nm. We first fitted the resistance characteristics of the sample using Eqs.…”

Section: Model Fitting With P-mtj Samplementioning

confidence: 99%

Stochastic macromodel of magnetic tunnel junction resistance variation and critical current dependence on resistance variation for SPICE simulation

Choi

Song²

2017

Jpn. J. Appl. Phys.

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The resistance distribution of a magnetic tunnel junction (MTJ) shows nonuniformity according to various MTJ parameters. Moreover, this resistance variation leads to write-current density variation, which can cause serious problems when designing peripheral circuits for spin transfer torque magnetoresistance random access memory (STT-MRAM) and commercializing gigabit STT-MRAM. Therefore, a macromodel of MTJ including resistance, tunneling magnetoresistance ratio (TMR), and critical current variations is required for circuit designers to design MRAM peripheral circuits, that can overcome the various effects of the variations, such as write failure and read failure, and realize STT-MRAM. In this study, we investigated a stochastic behavior macromodel of the write current dependence on the MTJ resistance variation. The proposed model can possibly be used to analyze the write current density in relation to the resistance and TMR variations of MTJ with various parameter variations. It can be very helpful for designing STT-MRAM circuits and simulating the operation of STT-MRAM devices considering MTJ variations.

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“…Due to limitations of the post-process, the required spin-polarized current is in the order of 1 mA. State-of-the-art PMA-STT processes require currents as low as 50 μA [11], though.…”

Section: Non-volatile Registersmentioning

confidence: 99%

Potential Applications Based on NVM Emerging Technologies

Senni¹,

Brum²,

Torres³

et al. 2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

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Energy efficiency is a critical figure of merit for battery-powered applications. Today's embedded systems suffer from significant increase of power consumption essentially due to a high leakage current in advanced technology node. A significant portion of the total power consumption is spent into memory systems because of an increasing trend of embedded volatile memory area among the building components in Systemon-Chips (SoCs). That is why new Non-Volatile Memory (NVM) technologies are considered as a potential solution to solve the energy efficiency issue. Among these NVM technologies, Magnetic RAM (MRAM) is a promising candidate to replace current memories since it combines non-volatility, high scalability, high density, low latency and low leakage. This paper explores use of MRAM into a memory hierarchy (from cache memory to register) of a processor-based system analyzing both performance and energy consumption. I.

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Design and fabrication of a perpendicular magnetic tunnel junction based nonvolatile programmable switch achieving 40% less area using shared-control transistor structure

Cited by 11 publications

References 17 publications

Design of a cost-efficient controller for realizing a data-shift-minimized nonvolatile field-programmable gate array

Design of a cost-efficient controller for realizing a data-shift-minimized nonvolatile field-programmable gate array

Stochastic macromodel of magnetic tunnel junction resistance variation and critical current dependence on resistance variation for SPICE simulation

Potential Applications Based on NVM Emerging Technologies

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