23% faster program and 40% energy reduction of carbon nanotube non-volatile memory with over 1011 endurance

Ning, Sheyang; Iwasaki, Takaya; Shimomura, Koichiro; Koh, Jung‐Hyuk; Rosendale, Glen; Manning, Monte; Viviani, Darlene; Rueckes, Thomas; Takeuchi, Ken

doi:10.1109/vlsit.2014.6894384

Cited by 9 publications

(11 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Fig. 3(a) and (b) [21] show that the distance between CNTs can be decreased and increased during set and reset, respectively, which controls the NRAM cell tunneling current and cell resistance. In detail, the cell resistance is low when the CNTs are close together and the tunneling current is high.…”

Section: Characteristics Of Nram Cell Arraymentioning

confidence: 99%

“…Fig. 4 shows measured NRAM single cell set and reset waveforms [21]. NRAM has characteristics of low current and low energy program compared with other emerging memories [8]- [10].…”

Section: Characteristics Of Nram Cell Arraymentioning

confidence: 99%

“…Lastly, the conclusions are given in Section VII. [21]. The resistance is low when CNTs are contact.…”

mentioning

confidence: 99%

“…4. NRAM single cell set and reset pulse waveforms [21]. NRAM has characteristics of low current and low energy program.…”

mentioning

confidence: 99%

See 3 more Smart Citations

Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory

Ning

Iwasaki

Tanakamaru

et al. 2016

IEEE J. Solid-State Circuits

Self Cite

View full text Add to dashboard Cite

A novel error correction scheme, called reset-checkreverse-flag (RCRF), is proposed to improve the reliability of storage class memories (SCMs). RCRF divides the conventional Bose-Chaudhuri-Hocquenghem (BCH) code length into multiple subsections. One flag bit is added to each subsection to correct program errors. By reversing the flag bit and user data, at least one reset error in each subsection can be recovered. A 4 Mbit carbon nanotube (CNT) based nano-random access memory (NRAM) cell array is measured to verify this scheme. During 10 8 write cycles, it is demonstrated that RCRF reduces the program bit error rate (BER) by 50% and only requires 0.4% extra array area for the flag bits. Next, BCH ECC is applied after RCRF to correct the remaining errors. Compared with the conventional BCH ECC-only approach, the proposed combination of RCRF and BCH ECC reduces parity overhead by 35% and ECC decoding latency by 16%. Therefore, RCRF is especially suited for read-intensive types of data storage, such as video and audio. On the other hand, for high endurance applications, RCRF and BCH ECC is also effective to improve the cycling reliability of resistive memories, and 50 times endurance extension is demonstrated for a 50 nm Al x O y resistive RAM (ReRAM) test chip.Index Terms-Carbon nanotube, emerging memory, error correcting code, memory controller, non-volatile memory, NRAM, reliability, solid-state drive, storage class memory.

show abstract

Section: Characteristics Of Nram Cell Arraymentioning

confidence: 99%

“…Fig. 4 shows measured NRAM single cell set and reset waveforms [21]. NRAM has characteristics of low current and low energy program compared with other emerging memories [8]- [10].…”

Section: Characteristics Of Nram Cell Arraymentioning

confidence: 99%

See 2 more Smart Citations

Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory

Ning

Iwasaki

Tanakamaru

et al. 2016

IEEE J. Solid-State Circuits

Self Cite

View full text Add to dashboard Cite

show abstract

“…Emerging non-volatile memories, such as nano-random access memory (NRAM), resistive random access memory (ReRAM), and phase-change memory (PRAM) have advantages of fast program, large program endurance, and low program voltage compared with conventional non-volatile memory, such as NAND flash. [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18] Different physical mechanisms can be found on these emerging non-volatile memories. In specific, binary data "0" and "1" is stored in ReRAM by switching the cell resistance between high resistance state (HRS) and low resistance state (LRS).…”

Section: Introductionmentioning

confidence: 99%

Carbon nanotube memory cell array program error analysis and tradeoff between reset voltage and verify pulses

Ning

Iwasaki

Hachiya

et al. 2016

Jpn. J. Appl. Phys.

Self Cite

View full text Add to dashboard Cite

In emerging non-volatile memories, nano-random access memory (NRAM) has advantages of small program current and high endurance compared with resistive RAM (ReRAM) and phase-change RAM (PRAM). This work comprehensively investigates NRAM set and reset program characteristics by measuring a 116 nm 4 Mbit NRAM cell array. Specifically, reset is found more dependent on reset voltage than reset current. Next, NRAM set and reset bit error rates (BERs) have less significant reduction compared with the increased ratio of set and reset pulse widths. The reset BER can also be reduced by applying multiple reset pulses. Moreover, 108 write cycles are measured on 256 bytes NRAM cells, no wear-out or broken cell is found. Finally, the program characteristics of two verify-reset schemes are compared. The maximum verify-reset voltage can be reduced by increasing the number of reset pulses.

show abstract

NRAM: a disruptive carbon-nanotube resistance-change memory

Gilmer¹,

Rueckes²,

Cleveland³

2018

Nanotechnology

View full text Add to dashboard Cite

Advanced memory technology based on carbon nanotubes (CNTs) (NRAM) possesses desired properties for implementation in a host of integrated systems due to demonstrated advantages of its operation including high speed (nanotubes can switch state in picoseconds), high endurance (over a trillion), and low power (with essential zero standby power). The applicable integrated systems for NRAM have markets that will see compound annual growth rates (CAGR) of over 62% between 2018 and 2023, with an embedded systems CAGR of 115% in 2018-2023 (http://bccresearch.com/pressroom/smc/bcc-research-predicts:-nram-(finally)-to-revolutionize-computer-memory). These opportunities are helping drive the realization of a shift from silicon-based to carbon-based (NRAM) memories. NRAM is a memory cell made up of an interlocking matrix of CNTs, either touching or slightly separated, leading to low or higher resistance states respectively. The small movement of atoms, as opposed to moving electrons for traditional silicon-based memories, renders NRAM with a more robust endurance and high temperature retention/operation which, along with high speed/low power, is expected to blossom in this memory technology to be a disruptive replacement for the current status quo of DRAM (dynamic RAM), SRAM (static RAM), and NAND flash memories.

show abstract

23% faster program and 40% energy reduction of carbon nanotube non-volatile memory with over 1011 endurance

Cited by 9 publications

References 0 publications

Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory

Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory

Carbon nanotube memory cell array program error analysis and tradeoff between reset voltage and verify pulses

NRAM: a disruptive carbon-nanotube resistance-change memory

Contact Info

Product

Resources

About