22nm FDSOI SRAM single event upset simulation analysis

Yuan, Jingshuang; Zhao, Yuanfu; Wang, Liang; Li, Tongde; Sui, Chenglong

doi:10.1088/1742-6596/1920/1/012069

Cited by 8 publications

(5 citation statements)

References 2 publications

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“…When the Q is high, the Q n is bound to be low, and vice versa. As shown in Figure 10, Q, as a sensitive node in SRAM circuit, is vulnerable to single event bombardment, resulting in logic flipping of the circuit [15]. M3 is selected as the single event injection device, and the Weibull current source model is added at the Q to simulate the SET current.…”

Section: T-sram Single Event Upsetmentioning

confidence: 99%

Single Event Upset Study of 22 nm Fully Depleted Silicon-on-Insulator Static Random Access Memory with Charge Sharing Effect

Yin,

Gao,

Wei

et al. 2023

Micromachines

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In this paper, the single event effect of 6T-SRAM is simulated at circuit level and device level based on a 22 nm fully depleted silicon-on-insulator (FDSOI) process, and the effects of charge sharing and bipolar amplification are considered in device-level simulation. The results demonstrate that, under the combined influence of these two effects, the circuit’s upset threshold and critical charge decreased by 15.4% and 23.5%, respectively. This indicates that the charge sharing effect exacerbates the single event effects. By analyzing the incident conditions of two different incident radius particles, it is concluded that the particles with a smaller incident radius have a worse impact on the SRAM circuit, and are more likely to cause the single event upset in the circuit, indicating that the ionization distribution generated by the incident particle affects the charge collection.

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Section: T-sram Single Event Upsetmentioning

confidence: 99%

Single Event Upset Study of 22 nm Fully Depleted Silicon-on-Insulator Static Random Access Memory with Charge Sharing Effect

Yin,

Gao,

Wei

et al. 2023

Micromachines

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“…It is known that a thinner SiO 2 BOX layer can lead to a milder TID effect [18,22]. The thicknesses of the BOX and the SOI body of the 28-nm FD SOI technology are 25-nm and 7-nm [23], and those are 20-nm and 6-nm in the 22-nm FD SOI technology node, respectively [24]. The BOX of the 22-nm process is 25% thinner than that of the 28-nm process, so a less positive charge will be deposited in the BOX of the 22-nm process during irradiation.…”

Section: Ro Type Relative Decrease In Frequencymentioning

confidence: 99%

Comparison of Total Ionizing Dose Effects in 22-nm and 28-nm FD SOI Technologies

Elash

Jin

et al. 2022

Electronics

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Total ionizing dose (TID) effects from Co-60 gamma ray and heavy ion irradiation were studied at the 22-nm FD SOI technology node and compared with the testing results from the 28-nm FD SOI technology. Ring oscillators (RO) designed with inverters, NAND2, and NOR2 gates were used to observe the output frequency drift and current draw. Experimental results show a noticeable increased device current draw and decreases in RO frequencies where NOR2 ROs have the most degradation. As well, the functionality of a 256 kb SRAM block and shift-register chains were evaluated during C0-60 irradiation. SRAM functionality deteriorated at 325 krad(Si) of the total dosage, while the FF chains remained functional up to 1 Mrad(Si). Overall, the 22-nm FD SOI results show better resilience to TID effects compared to the 28-nm FD SOI technology node.

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“…Reference [7] analyzed the influence of heavy ion incidence angle on SEU cross sections of the SRAM. Reference [8] compared the effects of different LETs and heavy ion incident positions on the SEU of a 22 nm Fully Depleted Silicon-On-Insulator (FDSOI) SRAM, and considered that whether SEU occurs depends on the peak value of transient current generated after heavy ion incidence.…”

Section: Introductionmentioning

confidence: 99%

Research on heavy ion irradiation effects on SOI SRAM

Li,

Hao,

Zhao

et al. 2023

J. Inst.

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SRAM based on SOI devices has been widely used in aerospace storage devices due to its good electrical characteristics and radiation resistance. However, with the development of semiconductor technology, the feature size of devices continues to shrink, and the irradiation effects of high-energy ions have become increasingly serious. Single event effect has become the biggest threat to the failure of the spacecraft. A mixed-simulation method was used to research the heavy ion irradiation effects on SOI SRAM. SRAM consists of two coupled inverters. Firstly, the voltage changes of the inverter and SRAM output nodes under heavy ion irradiation were compared and analyzed, then the influence of the device itself and heavy ion parameters on the single particle flipping effect of the SRAM is investigated, and finally the necessary conditions for the flipping of the stored information in the SRAM are discussed and derived. The results show that heavy ion incidence does not permanently change the final state of the inverter; devices in the off state in the SRAM will undergo information flipping only when they are irradiated by heavy ions, and the threshold voltage of the N-type MOSFET is lower than that of the P-type MOSFET; an increase in the penetration depth will accelerate the flipping speed of the SRAM, but when the LET is high, the influence of the penetration depth on the flipping speed decreases; the change of the stored information in the SRAM is the result of the combined effect of pulse width and pulse height.

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22nm FDSOI SRAM single event upset simulation analysis

Cited by 8 publications

References 2 publications

Single Event Upset Study of 22 nm Fully Depleted Silicon-on-Insulator Static Random Access Memory with Charge Sharing Effect

Single Event Upset Study of 22 nm Fully Depleted Silicon-on-Insulator Static Random Access Memory with Charge Sharing Effect

Comparison of Total Ionizing Dose Effects in 22-nm and 28-nm FD SOI Technologies

Research on heavy ion irradiation effects on SOI SRAM

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