21.5-dBm Power-Handling 5-GHz Transmit/Receive CMOS Switch Realized by Voltage Division Effect of Stacked Transistor Configuration With Depletion-Layer-Extended Transistors (DETs)

Ohnakado, T.; Yamakawa, Satoshi; Murakami, Takeshi; Furukawa, Akihiko; Taniguchi, Eiji; Ueda, Hiroyuki; Suematsu, Noriharu; Oomori, Tatsuo

doi:10.1109/jssc.2004.825231

Cited by 55 publications

(19 citation statements)

References 8 publications

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“…A switch with P1 dB of 28.5 dBm and IL of 1.5 dB have been achieved at 2.4 GHz [7] using a parallel LC tank to connect the bulk. Another method to improve the linearity of RF switch is using stacked transistors [8]; however, this will deteriorate the insertion loss. This paper proposes a novel asymmetrical 2.4 GHz CMOS SPDT using ac-floating and dc-bias techniques [9].…”

Section: Introductionmentioning

confidence: 99%

An Asymmetrical Bulk Cmos Switch for 2.4 GHZ Application

Chen¹,

Yebing²

2017

PIER Letters

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Abstract-A novel asymmetrical single-pole double-throw (SPDT) switch for 2.4 GHz application with high power handle ability is developed. The novel asymmetrical topology is discussed. To increase the power capacity, ac-floating and dc-bias techniques are used. Using these techniques, a switch achieves a measured P1 dB of 20.5 dBm, an insertion loss (IL) of 1.16 dB and an isolation loss of 20.8 dB in TX mode; an insertion loss of 1.57 dB and isolation of 21.6 dB in RX mode. The circuit is fabricated using 3.3-V 0.35-µm DNW NMOS transistors in 0.18-µm bulk CMOS process.

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Section: Introductionmentioning

confidence: 99%

An Asymmetrical Bulk Cmos Switch for 2.4 GHZ Application

Chen¹,

Yebing²

2017

PIER Letters

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“…When operating in the receiver (R X ) mode, the insertion loss (IL) was too high, which the noise could be increased in the R X circuit. Using the CMOS T/R switch is not only conducive to digital, RF and analog functions in single-chip integration, the more effectively but also reduce costs [1][2][3][4].…”

Section: Introductionmentioning

confidence: 99%

Low insertion loss Ka-band SPST switch using S-GCPW designs

Cho

Chiu

et al. 2012

2012 4th International High Speed Intelligent Communication Forum

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“…Owing to the intrinsic drawbacks of standard CMOS process in RF perspectives, viz., a low quality factor, lossy substrate of passive elements, and low breakdown voltage of active devices, the design of a T/R switch in CMOS with satisfactory performance is a challenging task. Nevertheless, there have been many attempts to design T/ R switches in CMOS over the last decade [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19]. A few novel design techniques such as minimizing or maximizing substrate resistance [1], stacking transistors [3], floating bodies [4,5], and stacking transistors together with floating bodies [19] have been devised for CMOS T/R switches.…”

Section: Introductionmentioning

confidence: 99%

“…Nevertheless, there have been many attempts to design T/ R switches in CMOS over the last decade [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19]. A few novel design techniques such as minimizing or maximizing substrate resistance [1], stacking transistors [3], floating bodies [4,5], and stacking transistors together with floating bodies [19] have been devised for CMOS T/R switches. Among them, the body-floating techniques that increase significantly power-handling capability of CMOS T/R switches have attracted our attention [7,8].…”

Section: Introductionmentioning

confidence: 99%

A comparative study of two techniques for improving power-handling capability of CMOS T/R switches

Zhang

Yeo

et al. 2010

Int J RF and Microwave Comp Aid Eng

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This article proposes an asymmetric topology for transmit/receive (T/R) switches and more importantly presents a comparative study of both LC-tuned and resistive body-floating techniques for improving the power-handling capability of the T/R switches in the same 0.18-lm triple-well CMOS. It is shown from simulations and measurements that the switches adopting either technique achieve comparable performances. For instance, the switch employing the LC-tuned body-floating technique exhibits insertion loss of 1.5 dB, isolation of 23.5 dB, and power-handling capability of 22.5 dBm at 5.2 GHz, whereas the switch using the resistive body-floating technique exhibits insertion loss of 1.3 dB, isolation of 24 dB, and power-handling capability of 22.2 dBm, respectively. Therefore, one can conclude that the asymmetric topology with the resistive body-floating technique is more suitable for designing T/R switches for wireless local area network applications as it consumes smaller silicon area.

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21.5-dBm Power-Handling 5-GHz Transmit/Receive CMOS Switch Realized by Voltage Division Effect of Stacked Transistor Configuration With Depletion-Layer-Extended Transistors (DETs)

Cited by 55 publications

References 8 publications

An Asymmetrical Bulk Cmos Switch for 2.4 GHZ Application

An Asymmetrical Bulk Cmos Switch for 2.4 GHZ Application

Low insertion loss Ka-band SPST switch using S-GCPW designs

A comparative study of two techniques for improving power-handling capability of CMOS T/R switches

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