21.2: <i>Distinguished Paper</i>: 55‐inch OLED TV using InGaZnO TFTs with WRGB Pixel Design

Nam, Woo‐Jin; Shim, Jong-Sik; Shin, Hong-Jae; Kim, Jin-Mog; Ha, Woo-Suk; Park, Kwan-Ho; Kim, Hong-Gyu; Kim, Bum-Sik; Oh, Chang‐Ho; Ahn, Byung‐Chul; Kim, Bong-Chul; Cha, Soo-Youle

doi:10.1002/j.2168-0159.2013.tb06190.x

Cited by 52 publications

(30 citation statements)

References 4 publications

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“…In this paper, we introduced novel GIP circuit to realize the real time sensing and compensation process of OLED TVs. The external compensation method (ECM) compensates for the threshold voltage and mobility variation of TFTs . Using this method, we solve reliability issues caused by positive and negative biases, temperature, and current stress.…”

Section: Introductionmentioning

confidence: 99%

Integrated gate driver circuit technology with IGZO TFT for sensing operation

Kim¹,

Noh²,

Ban³

et al. 2019

J Soc Info Display

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In this paper, we propose a new integrated gate driver circuit for random sensing operation of external compensated organic light‐emitting diode (OLED) display using oxide thin‐film transistor (TFT). Using this technology, we successfully launched 55‐inch and 65‐inch ultrahigh definition OLED TVs with gate in panel (GIP) circuit. The structure of the existing OLED TVs implemented gate signals through the gate integrated circuits (ICs) attached to the left and right sides of the panel. The structure using the gate IC was inferior to the panel structure using the GIP in terms of process and product design and cost. Thus, we propose a new oxide GIP circuit for OLED TV. Like the previous gate IC model, the proposed GIP circuit successfully implemented the random sensing function during the display operation. This GIP circuit is also designed to overcome the problems caused by the negative Vth characteristics of the oxide device.

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Section: Introductionmentioning

confidence: 99%

Integrated gate driver circuit technology with IGZO TFT for sensing operation

Kim¹,

Noh²,

Ban³

et al. 2019

J Soc Info Display

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“…More than 10 years since its discovery, indium gallium zinc oxide (IGZO) metal‐oxide semiconductor has entered the display industry . IGZO is typically deposited by sputtering from a solid target, which requires high vacuum and comes with inherent difficulties with homogeneity and compositional control over large areas.…”

Section: Introductionmentioning

confidence: 99%

Large‐area spatial atomic layer deposition of amorphous oxide semiconductors at atmospheric pressure

et al. 2019

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Indium gallium zinc oxide (IGZO) is deposited using plasma‐enhanced spatial atomic layer deposition (sALD) on substrates as large as 32 × 35 cm2. Excellent uniformity and thickness control leads to high‐performing and stable coplanar top‐gate self‐aligned (SA) thin‐film transistors (TFTs). The integration of a sALD‐deposited aluminum oxide buffer layer into the TFT stack further improves uniformity and stability. The results demonstrate the viability of atmospheric sALD as a novel deposition technique for the flat‐panel display industry.

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“…The positive bias stress (PBS)-induced instability is of special importance in terms of the active matrix organic light emitting diode (AMOLED) displays because applying both the positive gate-to-source voltage (V GS ) and positive drain-to-source voltage (V DS ) corresponds with the driving condition of AMOLED [3][4][5]. Although various V GS /V DS conditions including the high V DS need to be investigated for optimizing the driving scheme of the AMOLED backplane driven by a-IGZO TFTs, most of the previous works have been focused on the cases of V GS higher than or equal to V DS [6][7][8].…”

Section: Introductionmentioning

confidence: 99%

Comparative Analysis on Positive Bias Stress-Induced Instability under High V_GS/Low V_DSand Low V_GS/High V_DSin Amorphous InGaZnO Thin-Film Transistors

Kang¹,

Jang²,

Kim³

et al. 2015

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Positive bias stress-induced instability in amorphous indium-gallium-zinc-oxide (a-IGZO) bottom-gate thin-film transistors (TFTs) was investigated under high V GS /low V DS and low V GS /high V DS stress conditions through incorporating a forward/reverse V GS sweep and a low/high V DS readout conditions. Our results showed that the electron trapping into the gate insulator dominantly occurs when high V GS /low V DS stress is applied. On the other hand, when low V GS /high V DS stress is applied, it was found that holes are uniformly trapped into the etch stopper and electrons are locally trapped into the gate insulator simultaneously. During a recovery after the high V GS /low V DS stress, the trapped electrons were detrapped from the gate insulator. In the case of recovery after the low V GS /high V DS stress, it was observed that the electrons in the gate insulator diffuse to a direction toward the source electrode and the holes were detrapped to out of the etch stopper. Also, we found that the potential profile in the a-IGZO bottom-gate TFT becomes complicatedly modulated during the positive V GS /V DS stress and the recovery causing various threshold voltages and subthreshold swings under various read-out conditions, and this modulation needs to be fully considered in the design of oxide TFT-based active matrix organic light emitting diode display backplane.

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21.2: Distinguished Paper: 55‐inch OLED TV using InGaZnO TFTs with WRGB Pixel Design

Cited by 52 publications

References 4 publications

Integrated gate driver circuit technology with IGZO TFT for sensing operation

Integrated gate driver circuit technology with IGZO TFT for sensing operation

Large‐area spatial atomic layer deposition of amorphous oxide semiconductors at atmospheric pressure

Comparative Analysis on Positive Bias Stress-Induced Instability under High V_GS/Low V_DSand Low V_GS/High V_DSin Amorphous InGaZnO Thin-Film Transistors

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21.2: Distinguished Paper: 55‐inch OLED TV using InGaZnO TFTs with WRGB Pixel Design

Cited by 52 publications

References 4 publications

Integrated gate driver circuit technology with IGZO TFT for sensing operation

Integrated gate driver circuit technology with IGZO TFT for sensing operation

Large‐area spatial atomic layer deposition of amorphous oxide semiconductors at atmospheric pressure

Comparative Analysis on Positive Bias Stress-Induced Instability under High VGS/Low VDSand Low VGS/High VDSin Amorphous InGaZnO Thin-Film Transistors

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Comparative Analysis on Positive Bias Stress-Induced Instability under High V_GS/Low V_DSand Low V_GS/High V_DSin Amorphous InGaZnO Thin-Film Transistors