20Gbps C-Based Complex Event Processing

Inoue, Hiroaki; Takenaka, Takashi; Motomura, Masato

doi:10.1109/fpl.2011.27

Cited by 10 publications

(3 citation statements)

References 12 publications

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“…Furthermore, FPGA solutions in the context of databases have been proposed for sorting [Koch and Torresen 2011], XML filtering [Moussalli et al 2011], or high-speed event processing [Inoue et al 2011]. Nevertheless, those examples all confirm the observation of Chung et al [2011]: FPGAs still lack essential abstractions that have become pervasive in general-purpose computers; rather, most systems are developed in an ad-hoc manner for just one particular problem setting.…”

Section: Related Workmentioning

confidence: 74%

Parallelizing Data Processing on FPGAs with Shifter Lists

Woods

Alonso

Teubner

2015

ACM Trans. Reconfigurable Technol. Syst.

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Parallelism is currently seen as a mechanism to minimize the impact of the power and heat dissipation problems encountered in modern hardware. Data parallelism-based on partitioning the data-and pipeline parallelism-based on partitioning the computation-are the two main approaches to leverage parallelism on a wide range of hardware platforms.Unfortunately, not all data processing problems are susceptible to either of those strategies. An example is the skyline operator [Börzsönyi et al. 2001], which computes the set of Pareto-optimal points within a multidimensional dataset. Existing approaches to parallelize the skyline operator are based on data parallelism. As a result, they suffer from a high overhead when merging intermediate results because of the lack of a global view of the problem inherent to partitioning the input data.In this article, we show how to combine pipeline with data parallelism on a Field-Programmable Gate Array (FPGA) for a more efficient utilization of the available hardware parallelism. As we show in our experiments, skyline computation using our proposed technique scales linearly with the number of processing elements, and the performance we achieve on a rather small FPGA is comparable to that of a 64-core high-end server running a state-of-the-art data parallel implementation of skyline [Park et al. 2009].The proposed approach to parallelize the skyline operator can be generalized to a wider range of data processing problems. We demonstrate this through a novel, highly parallel data structure, a shifter list, that can be efficiently implemented on an FPGA. The resulting template is easy to parametrize to implement a variety of computationally intensive operators such as frequent items, n-closest pairs, or K-means.

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Section: Related Workmentioning

confidence: 74%

Parallelizing Data Processing on FPGAs with Shifter Lists

Woods

Alonso

Teubner

2015

ACM Trans. Reconfigurable Technol. Syst.

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“…Here, function F1 is used twice. In a change-point analysis operation [8], input event ev and output event evout each contain two data items: time and price. Argument arg contains three data items: trend (for the direction of the smoothed polygonal line), last_time, and last_price (i.e., time and price data for the previous event).…”

Section: A Language Overviewmentioning

confidence: 99%

C-Based Complex Event Processing on Reconfigurable Hardware

Inoue

Takenaka

Motomura

2013

IEEE Trans. VLSI Syst.

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This briefpresents an efficient complex event-processing framework, designed to process a large number of sequential events on field-programmable gate arrays (FPGAs). Unlike conventional structured query language based approaches, our approach features logic automation constructed with a new C-based event language that supports regular expressions on the basis of C functions, so that a wide variety of event-processing applications can be efficiently mapped to FPGAs. Evaluations on an FPGA-based network interface card show that we can achieve 12.3 times better event-processing performance than does a CPU software in a financial trading application.

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“…Although CPU-based CEP systems achieve sophisticated event processing, they suffer from poor event processing performance. FPGAs are the possible reconfigurable hardware alternative in order to accelerate event processing (Inoue et al, 2011). Specific to batch processing, MapReduce (Apache, 2014) is a programming model and an associated implementation for processing and generating large data sets with a parallel and distributed approach.…”

Section: Big Data Storage and Processingmentioning

confidence: 99%

A survey on big data processing infrastructure: evolving role of FPGA

Nunna

Mehdipour

Trouvé

et al. 2015

IJBDI

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In today's commercial world, information is becoming a major economic resource thus leading to a statement -Information is wealth. It is a technical challenge for computer systems in managing and analyzing the large volumes of data coming from a variety of resources continuously over a period. Experts are in a mood of moving towards alternative hardware platforms for achieving high-speed data processing and analysis especially for streaming applications. In this paper, (a) existing trends in big data processing and the necessary systems involved are studied by performing a survey on available platforms, (b) recommended features and suitable hardware systems are proposed based on the operations involved in the processing. Investigation shows that, in combination with CPU and along with GPU, FPGA is a possible alternative. It can be a part of the heterogeneous platform featuring parallelism, pipelining and high performance for the operations involved in big data processing.

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20Gbps C-Based Complex Event Processing

Cited by 10 publications

References 12 publications

Parallelizing Data Processing on FPGAs with Shifter Lists

Parallelizing Data Processing on FPGAs with Shifter Lists

C-Based Complex Event Processing on Reconfigurable Hardware

A survey on big data processing infrastructure: evolving role of FPGA

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