20.3 A feedforward controlled on-chip switched-capacitor voltage regulator delivering 10W in 32nm SOI CMOS

Andersen, Tom Løgstrup; Krismer, Florian; Kolar, Johann W.; Toifl, Thomas; Menolfi, Christian; Kuli, Lukas; Morf, Thomas; Kossel, Marcel; Brandii, Matthias; Francese, Pier Andrea

doi:10.1109/isscc.2015.7063076

Cited by 37 publications

(22 citation statements)

References 2 publications

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“…In particular, it supports the realization of fine-grained power management with multiple independent voltage/frequency domains. Thanks to the progress in developing integrated voltage regulators [1,7,29,30], each domain can correspond to an individual ESP tile, thus providing fine granularity both in time and space. Each regulator is managed through a dedicated controller for dynamic voltage-frequency scaling.…”

Section: A Scalable Architecturementioning

confidence: 99%

“…In particular, each accelerator may be activated by a software application only when it is necessary to execute its particular function. Thanks to new technologies for fine-grain dynamic power management [1,7,29,30], it is possible to power up only those SoC components needed to run the current workload. It is this ability of independent activation of selected specialized components that makes parallel heterogeneous architectures a value proposition to preserve the progress of the semiconductor industry in the so-called "age of dark silicon", when power limitations are stringent and homogeneous multicore scaling has hit diminished returns [13].…”

Section: Introductionmentioning

confidence: 99%

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Invited - The case for embedded scalable platforms

Carloni

2016

Proceedings of the 53rd Annual Design Automation Conference

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Heterogeneous system-on-chip (SoC) architectures are emerging as a fundamental computing platform across a variety of domains, from mobile to cloud computing. Heterogeneity, however, increases design complexity in terms of hardware-software interactions, access to shared resources, and diminished regularity of the design. Embedded Scalable Platforms are a novel approach to SoC design and programming that addresses these design-complexity challenges by combining an architecture and a methodology. The flexible socketed architecture simplifies the integration of heterogeneous components by balancing regularity and specialization. The companion methodology raises the level of abstraction to system-level design, thus promoting closer collaboration among software programmers and hardware engineers. The architecture is supported by a scalable communication infrastructure. The methodology leverages compositional design-space exploration with high-level synthesis. The case for Embedded Scalable Platforms is made based on experiments on the development of various full-system prototypes and experience in teaching these concepts in a new graduate course.

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Section: A Scalable Architecturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Invited - The case for embedded scalable platforms

Carloni

2016

Proceedings of the 53rd Annual Design Automation Conference

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“…Request permissions from permissions@acm.org. come the focus of many research works [1,8,31,33] Typical IVRs are switching regulators that store energy in capacitors and/or inductors and deliver that energy at a potential controlled by a switching signal. Die-integrated switchedcapacitor regulators boast fast transient response, high peak efficiency (>90%), and minimal technology requirements.…”

Section: Introductionmentioning

confidence: 99%

“…Die-integrated switchedcapacitor regulators boast fast transient response, high peak efficiency (>90%), and minimal technology requirements. Efforts have been made to preserve such efficiency while delivering sufficient power densities [1,10]. Switched-inductor regulators, on the other hand, naturally support higher power densities.…”

Section: Introductionmentioning

confidence: 99%

An FPGA-based infrastructure for fine-grained DVFS analysis in high-performance embedded systems

Mantovani

Cota

Tien

et al. 2016

Proceedings of the 53rd Annual Design Automation Conference

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Emerging technologies provide SoCs with fine-grained DVFS capabilities both in space (number of domains) and time (transients in the order of tens of nanoseconds). Analyzing these systems requires cycle-accurate accounting of rapidly-changing dynamics and complex interactions among accelerators, interconnect, memory, and OS. We present an FPGA-based infrastructure that facilitates such analyses for high-performance embedded systems. We show how our infrastructure can be used to first generate SoCs with looselycoupled accelerators, and then perform design-space exploration considering several DVFS policies under full-system workload scenarios, sweeping spatial and temporal domain granularity.

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“…The disadvantages of ReSC converters are mainly the need for inductors and explicit bypass capacitance. Bypass capacitors can be eliminated in SC converters by using a large number of interleaved phases [2], [6]; however, in ReSC an inductor is required for each phase which presents a limit on the number of phases. Multi-phase interleaving is also used in inductive converters, most prominently in microprocessor voltage regulators [7], [8] where interleaving is used to reduce output voltage ripple and improve transient performance.…”

Section: Introductionmentioning

confidence: 99%

Design aspects of multi-phase interleaved resonant switched-capacitor converters with mm-scale air-core inductors

Schaef

Reese

Sullivan

et al. 2015

2015 IEEE 16th Workshop on Control and Modeling for Power Electronics (COMPEL)

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This work explores design aspects of resonant switched-capacitor converters with respect to multi-phase interleaving and inductor design. In high-density or silicon-integrated ReSC converters, interleaving can not only significantly improve output voltage ripple but also efficiency and power density by reducing bypass capacitance requirements and thus providing more area for flying capacitance. An analytical approach to analyze voltage ripple in multi-phase designs is presented. Moreover, a design methodology for miniature air-core inductors for a multiphase ReSC converter is described and design trade-offs are discussed. Results of the ripple analysis and inductor design are compared with measurement results from a three phase ReSC prototype IC in 180 nm CMOS.

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20.3 A feedforward controlled on-chip switched-capacitor voltage regulator delivering 10W in 32nm SOI CMOS

Cited by 37 publications

References 2 publications

Invited - The case for embedded scalable platforms

Invited - The case for embedded scalable platforms

An FPGA-based infrastructure for fine-grained DVFS analysis in high-performance embedded systems

Design aspects of multi-phase interleaved resonant switched-capacitor converters with mm-scale air-core inductors

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