20.3 A 100nA-to-2mA successive-approximation digital LDO with PD compensation and sub-LSB duty control achieving a 15.1ns response time at 0.5V

Salem, Loai G.; Warchall, Julian; Mercier, Patrick P.

doi:10.1109/isscc.2017.7870400

Cited by 44 publications

(17 citation statements)

References 4 publications

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“…Therefore, V OUT increases continuously and an unwanted large overshoot voltage was generated. As a result, unwanted overshoot and undershoot voltages were generated until V OUT settled to V REF at time T 3 , generating ringing and increasing the setting time [2][3][4][5][6][7].…”

Section: Proposed Coarse-fine Digital Lowdropout Regulatormentioning

confidence: 99%

“…Digital low-dropout (D-LDO) regulators are used in portable devices, biomedical devices, and internet-of-things applications [1][2][3][4][5][6][7][8][9][10] because of their lower supply-voltage, small power-transistors, stability, and compatible processes. However, D-LDO features a long settling time and a ringing problem while settling the output voltage at large load transitions.…”

Section: Introductionmentioning

confidence: 99%

“…Several D-LDOs have been developed to reduce settling time [2][3][4][5][6][7][8][9][10][11][12] and D-LDOs with proportional-integral (PI) control removed the ringing. These devices used a level-crossing ADC with numerous reference voltages [2] and a delay line ADC with an analog voltage-to-current converter [3].…”

Section: Introductionmentioning

confidence: 99%

“…Moreover, the PI control and SLC estimator were complex because they required an additional mathematical operator. Successive approximation register (SAR)-type D-LDO [5] improved the transient response with a binary PMOS array and removed ringing by using a proportional-derivative (PD) compensator. However, when the load current is significantly changed, the PD compensator increases or decreases the PMOS array current to match the load current.…”

Section: Introductionmentioning

confidence: 99%

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Low‐ripple coarse‐fine digital low‐dropout regulator without ringing in the transient state

Woo

Yang

2020

ETRI Journal

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Herein, a low-ripple coarse-fine digital low-dropout regulator (D-LDO) without ringing in the transient state is proposed. Conventional D-LDO suffers from a ringing problem when settling the output voltage at a large load transition, which increases the settling time. The proposed D-LDO removes the ringing and reduces the settling time using an auxiliary power stage which adjusts its output current to a load current in the transient state. It also achieves a low output ripple voltage using a comparator with a complete comparison signal. The proposed D-LDO was fabricated using a 65-nm CMOS process with an area of 0.0056 μm 2. The undershoot and overshoot were 47 mV and 23 mV, respectively, when the load current was changed from 10 mA to 100 mA within an edge time of 20 ns. The settling time decreased from 2.1 μs to 130 ns and the ripple voltage was 3 mV with a quiescent current of 75 μA.

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Section: Proposed Coarse-fine Digital Lowdropout Regulatormentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Low‐ripple coarse‐fine digital low‐dropout regulator without ringing in the transient state

Woo

Yang

2020

ETRI Journal

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“…The fine-grained supply voltage management faces a real challenge. In contrast to analog low drop-out regulator (LDO), digital LDOs (DLDO) exhibiting ultra-low operating voltage [1][2][3][4][5][6]. Hence, the DLDO has been widely used in the low source supply voltage conditions and digital load circuits.…”

Section: Introductionmentioning

confidence: 99%

A Fast Transient Response Digital LDO with a TDC-Based Signal Converter

Zhang¹,

Wan²,

Geng³

et al. 2020

Electronics

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The digital low drop-out regulator (LDO) has been used widely in digital circuits for its low supply voltage characteristics. However, as the traditional digital LDOs regulate the output voltage code at a rate of 1 bit per clock cycle, the transient response speed is limited. This paper presents a digital LDO to improve transient response speed with a multi-bit conversion technique. The proposed technology uses a voltage sensor and a time-to-digital converter to convert the output voltage to digital codes. Based on a 65-nm CMOS process, the proposed DLDO reduces the settling time from 147.8 ns to 25.2 ns on average and the response speed is improved by about six times.

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