1996 Symposium on VLSI Circuits. Digest of Technical Papers
DOI: 10.1109/vlsic.1996.507711
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2 V/100 ns 1 T/1 C nonvolatile ferroelectric memory architecture with bitline-driven read scheme and non-relaxation reference cell

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“…After the tiny signal is captured and amplified by the sense amplifier (SA), the charge of the ferroelectric capacitor is converted to the logic "0" or "1" to be processed. In the operation of read/write, the bitline-driven architecture [8][9] will frequently charge the parasite capacitance of the bitline, causing a high peak current called surge current. The existence of surge current in the read/write process will affect the performance on power consumption and read/write operation of FeRAM from the perspective of long-time work.…”
Section: Introductionmentioning
confidence: 99%
“…After the tiny signal is captured and amplified by the sense amplifier (SA), the charge of the ferroelectric capacitor is converted to the logic "0" or "1" to be processed. In the operation of read/write, the bitline-driven architecture [8][9] will frequently charge the parasite capacitance of the bitline, causing a high peak current called surge current. The existence of surge current in the read/write process will affect the performance on power consumption and read/write operation of FeRAM from the perspective of long-time work.…”
Section: Introductionmentioning
confidence: 99%