2-Mb Embedded Phase Change Memory With 16-ns Read Access Time and 5-Mb/s Write Throughput in 90-nm BCD Technology for Automotive Applications

Carissimi, Marcella; Mukherjee, Rajarshi; Tyagi, Vivek; Disegni, F.; Manfre, D.; Torti, C.; Gallinari, D.; Rossi, Silvano R.; Gambero, A.; Brambilla, D.; Zuliani, P.; Zurla, Riccardo; Cabrini, A.; Torelli, G.; Pasotti, M.; Auricchio, C.; Calvetti, E.; Capecchi, L.; Croce, L.; Zanchi, S.; Rana, Vikas; Mishra, Prabhat

doi:10.1109/lssc.2019.2935874

Cited by 6 publications

(6 citation statements)

References 7 publications

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“…We performed the experimental activity on an embedded PCM (ePCM) test chip designed and manufactured by STMicroelectronics [ 20 ] in 90-nm smart power BCD technology featuring a specifically optimized Ge-rich Ge-Sb-Te (GST) alloy. The chip is intended for digital storage in automotive applications.…”

Section: Methodsmentioning

confidence: 99%

“…To improve the programming speed, A MIN could be chosen in relation to the target level. An estimation of mean programming time is also provided in Table 2 , which takes into account of the averaged durations of SET and RESET pulses only, assuming T ON,S = 150 ns, as cell readout time is negligible in case the programming algorithm is performed on an embedded system [ 20 ]. Every cell was correctly programmed within the maximum 100 iterations.…”

Section: A Programming Algorithm For Aimcmentioning

confidence: 99%

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Characterization and Programming Algorithm of Phase Change Memory Cells for Analog In-Memory Computing

et al. 2021

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In this paper, a thorough characterization of phase-change memory (PCM) cells was carried out, aimed at evaluating and optimizing their performance as enabling devices for analog in-memory computing (AIMC) applications. Exploiting the features of programming pulses, we discuss strategies to reduce undesired phenomena that afflict PCM cells and are particularly harmful in analog computations, such as low-frequency noise, time drift, and cell-to-cell variability of the conductance. The test vehicle is an embedded PCM (ePCM) provided by STMicroelectronics and designed in 90-nm smart power BCD technology with a Ge-rich Ge-Sb-Te (GST) alloy for automotive applications. On the basis of the results of the characterization of a large number of cells, we propose an iterative algorithm to allow multi-level cell conductance programming, and its performances for AIMC applications are discussed. Results for a group of 512 cells programmed with four different conductance levels are presented, showing an initial conductance spread under 6%, relative current noise less than 9% in most cases, and a relative conductance drift of 15% in the worst case after 14 h from the application of the programming sequence.

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Section: Methodsmentioning

confidence: 99%

Section: A Programming Algorithm For Aimcmentioning

confidence: 99%

Characterization and Programming Algorithm of Phase Change Memory Cells for Analog In-Memory Computing

et al. 2021

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“…Its target applications are in the automotive field, where it is used as a digital storage element, with 8 independent 256-kB macrocells and the required analog circuitry. Each ePCM elementary cell is addressed by an NMOS selector [8] and its area occupation is 0.19 µm 2 . The chip is accessible through a custom evaluation board designed specifically for testing purposes.…”

Section: Pcm Characterization and Numerical Modelingmentioning

confidence: 99%

Phase-Change Memory in Neural Network Layers with Measurements-based Device Models

Paolino

Antolini

Pareschi

et al. 2022

2022 IEEE International Symposium on Circuits and Systems (ISCAS)

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The search for energy efficient circuital implementations of neural networks has led to the exploration of phasechange memory (PCM) devices as their synaptic element, with the advantage of compact size and compatibility with CMOS fabrication technologies. In this work, we describe a methodology that, starting from measurements performed on a set of real PCM devices, enables the training of a neural network. The core of the procedure is the creation of a computational model, sufficiently general to include the effect of unwanted nonidealities, such as the voltage dependence of the conductances and the presence of surrounding circuitry. Results show that, depending on the task at hand, a different level of accuracy is required in the PCM model applied at train-time to match the performance of a traditional, reference network. Moreover, the trained networks are robust to the perturbation of the weight values, up to 10% standard deviation, with performance losses within 3.5% for the accuracy in the classification task being considered and an increase of the regression RMS error by 0.014 in a second task. The considered perturbation is compatible with the performance of state-of-theart PCM programming techniques.

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“…The chip is intended for digital storage in automotive applications and contains 8 independent 256-kB macrocells, together with voltage and current regulators. The ePCM elementary cell is based on an NMOS selector [5] and occupies 0.19 µm 2 of silicon area. A custom PCM evaluation board (designed ad-hoc for testing purposes) has been employed.…”

Section: Pcm Technology and Characterizationmentioning

confidence: 99%

Compressed Sensing by Phase Change Memories: Coping with Encoder non-Linearities

Paolino

Antolini

Pareschi

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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Several recent works have shown the advantages of using phase-change memory (PCM) in developing brain-inspired computing approaches. In particular, PCM cells have been applied to the direct computation of matrix-vector multiplications in the analog domain. However, the intrinsic nonlinearity of these cells with respect to the applied voltage is detrimental. In this paper we consider a PCM array as the encoder in a Compressed Sensing (CS) acquisition system, and investigate the effect of the non-linearity of the cells. We introduce a CS decoding strategy that is able to compensate for PCM nonlinearities by means of an iterative approach. At each step, the current signal estimate is used to approximate the average behaviour of the PCM cells used in the encoder. Monte Carlo simulations relying on a PCM model extracted from an STMicrolectronics 90 nm BCD chip validate the performance of the algorithm with various degrees of nonlinearities, showing up to 35 dB increase in median performance as compared to standard decoding procedures.

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2-Mb Embedded Phase Change Memory With 16-ns Read Access Time and 5-Mb/s Write Throughput in 90-nm BCD Technology for Automotive Applications

Cited by 6 publications

References 7 publications

Characterization and Programming Algorithm of Phase Change Memory Cells for Analog In-Memory Computing

Characterization and Programming Algorithm of Phase Change Memory Cells for Analog In-Memory Computing

Phase-Change Memory in Neural Network Layers with Measurements-based Device Models

Compressed Sensing by Phase Change Memories: Coping with Encoder non-Linearities

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