2 MB Array-Level Demonstration of STT-MRAM Process and Performance Towards L4 Cache Applications

Alzate, Juan G.; Hentges, P.; Jahan, R.; Littlejohn, Allison; Mainuddin, Mohammad; Ouellette, David; Pellegren, J. P.; Pramanik, Tanmoy; Puls, Conor; Quintero, Pedro A.; Rahman, Tauhidur; Arslan, Ümüt; Sekhar, Meenakshi; Sell, B.; Seth, M.; Smith, Andrew J.; Smith, Angeline Klemm; Wei, Lili; Wiegand, C.; Golonzka, O.; Hamzaoglu, Fatih; Bai, P.; Brockman, Justin; Chen, Y. J.; Das, Nilanjan; Fischer, K.; Ghani, T.; Heil, Philip Edward

doi:10.1109/iedm19573.2019.8993474

Cited by 88 publications

(37 citation statements)

References 5 publications

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“…The varying nature of the pinning level and characteristic pinning timescale indicate that the origin is most likely due to the inhomogeneities of the device microstructure. More specifically, defects in the interfacial MgO/CoFeB anisotropy have been reported to induce pinning in the STT switching process [ 31].…”

Section: Optimized Tmr Reading and Fast Stt Writing In Single Mtj Pillarmentioning

confidence: 99%

Nanoscale domain wall devices with magnetic tunnel junction read and write

et al. 2021

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Fast domain wall (DW) motion in magnetic nanostructures is crucial for future spintronic device concepts. However, a lack of energy-efficient, scalable and industry-relevant ways to electrically read and write DWs in nanoscale devices impedes practical applications. Here, we demonstrate that full electrical control of DW devices can be achieved by incorporating typical high DW velocity materials (i.e., Pt/Co and synthetic antiferromagnetic (SAF) Pt/Co/Ru/Co) into perpendicular magnetic tunnel junctions (pMTJs). We first show tunneling magnetoresistance (TMR) readout and efficient spin transfer torque (STT) writing, comparable to current STT-MRAM technology. Based on time-resolved measurements, we find faster STT switching dynamics in the SAF-based hybrid free layer than in conventional dual-MgO free layer while maintaining retention stability. We demonstrate the full operation of DW devices at nanoscale with MTJs enabling electrical read and write, and a heavy metal enabling spin orbit torque (SOT)-driven DW motion for information transmission. Beside implications to technology and applications, we show that these devices can be used as a tool to explore the physics of DW dynamics at nanoscale. Furthermore, using a SAFbased DW conduit has the potential to enhance device performance with faster and more reliable DW motion. This proof-of-concept offers a pathway to the technological development of highperformance and low-power DW-based devices.Magnetic domain walls (DW) could form a key ingredient in next generation logic and data storage devices [ 1,2] such as racetrack memory [ 3,4], spin logic [ 5,6,7,8] and neuromorphic computing [ 9,10,11].The discovery of high DW velocity governed by the Dzyaloshinskii-Moriya interaction (DMI) and spin-orbit torque (SOT) [ 12,13,14,15] in ultrathin magnetic layers on heavy metals, the additional exchange coupling torque (ECT) in synthetic antiferromagnetic (SAF) systems [ 16] and the angular momentum compensation in ferrimagnets [ 17], were major breakthroughs in the development of fast, high density, and low-energy devices based on DW motion. To enable these materials for practical application, DWs are required to be efficiently written and read at the nanoscale. However, to date, writing of DWs has mainly been performed through magnetic field-based approaches, and read out through either Hall bar devices or magnetic imaging techniques [ 5,8,9,12,13,17,14]. These schemes play a crucial role in characterizing material properties, but their applicability

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Section: Optimized Tmr Reading and Fast Stt Writing In Single Mtj Pillarmentioning

confidence: 99%

Nanoscale domain wall devices with magnetic tunnel junction read and write

et al. 2021

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“…Process variations in MTJ's geometrical parameters (e.g., CD, t FL , t TB ) and magnetic properties (e.g., H k and M s ) greatly contribute to the device-to-device variation in the switching behavior on top of the intrinsic switching stochasticity, as shown with silicon data in [35,36]. Our MTJ model takes into account process variation by introducing a Gaussian distribution to each of the above parameters.…”

Section: Process Variation (Pv)mentioning

confidence: 99%

Characterization, Modeling, and Test of Intermediate State Defects in STT-MRAM

Wu¹,

Rao²,

Taouil³

et al. 2021

Preprint

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<div>The manufacturing process of STT-MRAM requires unique steps to fabricate and integrate magnetic tunnel junction (MTJ) devices which are data-storing elements. Thus, understanding the defects in MTJs and their faulty behaviors are paramount for developing high-quality test solutions. This article applies the advanced device-aware test to intermediate (IM) state defects in MTJ devices based on silicon measurements and circuit simulations. An IM state manifests itself as an abnormal third resistive state, which differs from the two bi-stable states of MTJ. We performed silicon measurements on MTJ devices with diameter ranging from 60nm to 120nm; the results show that the occurrence probability of IM state strongly depends on the switching direction, device size, and bias voltage. We demonstrate that the conventional resistor- based fault modeling and test approach fails to appropriately model and test such a defect. Therefore, device-aware test is applied. We first physically model the defect and incorporate it into a Verilog-A MTJ compact model and calibrate it with silicon data. Thereafter, this model is used for a systematic fault analysis based on circuit simulations to obtain accurate and realistic faults in a pre-defined fault space. Our simulation results show that an IM state defect leads to intermittent write transition faults. Finally, we propose and implement a device-aware test solution to detect the IM state defect.</div>

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“…It is promising not only for standalone, but also for embedded memory applications as replacement of conventional volatile CMOS-based and nonvolatile flash memories in systems on chip. STT-MRAM can be integrated in a broad range of applications, from Internet-of-Things to automotive applications [ 3 ] and last level caches [ 8 , 9 , 10 ]. Recently, 1Gb standalone [ 11 ] and embedded STT-MRAM solutions [ 2 , 4 , 12 , 13 ] have been reported and STT-MRAM operation with a timing of a few nanoseconds has been demonstrated [ 8 ].…”

Section: Introductionmentioning

confidence: 99%

Optimization of a Spin-Orbit Torque Switching Scheme Based on Micromagnetic Simulations and Reinforcement Learning

et al. 2021

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Spin-orbit torque memory is a suitable candidate for next generation nonvolatile magnetoresistive random access memory. It combines high-speed operation with excellent endurance, being particularly promising for application in caches. In this work, a two-current pulse magnetic field-free spin-orbit torque switching scheme is combined with reinforcement learning in order to determine current pulse parameters leading to the fastest magnetization switching for the scheme. Based on micromagnetic simulations, it is shown that the switching probability strongly depends on the configuration of the current pulses for cell operation with sub-nanosecond timing. We demonstrate that the implemented reinforcement learning setup is able to determine an optimal pulse configuration to achieve a switching time in the order of 150 ps, which is 50% shorter than the time obtained with non-optimized pulse parameters. Reinforcement learning is a promising tool to automate and further optimize the switching characteristics of the two-pulse scheme. An analysis of the impact of material parameter variations has shown that deterministic switching can be ensured for all cells within the variation space, provided that the current densities of the applied pulses are properly adjusted.

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2 MB Array-Level Demonstration of STT-MRAM Process and Performance Towards L4 Cache Applications

Cited by 88 publications

References 5 publications

Nanoscale domain wall devices with magnetic tunnel junction read and write

Nanoscale domain wall devices with magnetic tunnel junction read and write

Characterization, Modeling, and Test of Intermediate State Defects in STT-MRAM

Optimization of a Spin-Orbit Torque Switching Scheme Based on Micromagnetic Simulations and Reinforcement Learning

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