2 Gbit/s transimpedance amplifier fabricated by 0.35 [micro sign]m CMOS technologies

Kuo, Chia Wei; Hsiao, Chao-Chil; Yang, Shih-Cheng; Chan, Yi‐Jen

doi:10.1049/el:20010797

Cited by 18 publications

(5 citation statements)

References 5 publications

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“…• parametric optimization: for a given transimpedance structure, find the combination of component parameters necessary for maximum bandwidth; • structural modification: for a given preamplifier architecture, make structural modifications, usually by adding elements such as inductors for shunt peaking [14] or capacitors as artificial loads or feedback [15]; • architectural exploration: use complex architectures such as bootstrap or common-gate input stages [16]. The basic transimpedance amplifier structure in a typical configuration is shown in Fig.…”

Section: A Receiver Circuit Synthesizable Modelmentioning

confidence: 99%

Systematic Simulation-Based Predictive Synthesis of Integrated Optical Interconnect

O’Connor

Tissafi-Drissi

Gaffiot

et al. 2007

IEEE Trans. VLSI Syst.

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Integrated optical interconnect has been identified by the ITRS as a potential solution to overcome predicted interconnect limitations in future systems-on-chip. However, the multiphysics nature of the design problem and the lack of a mature integrated photonic technology have contributed to severe difficulties in assessing its suitability. This paper describes a systematic, fully automated synthesis method for integrated microsource-based optical interconnect capable of optimally sizing the interface circuits based on system specifications, CMOS technology data, and optical device characteristics. The simulation-based nature of the design method means that its results are relatively accurate, even though the generation of each data point requires only 5 min on a 1.3-GHz processor. This method has been used to extract typical performance metrics (delay, power, interconnect density) for optical interconnect of length 2.5-20 mm in three predictive technologies at 65-, 45-, and 32-nm gate length.Index Terms-Integrated optical interconnect, multidomain design methods, synthesis.

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Section: A Receiver Circuit Synthesizable Modelmentioning

confidence: 99%

Systematic Simulation-Based Predictive Synthesis of Integrated Optical Interconnect

O’Connor

Tissafi-Drissi

Gaffiot

et al. 2007

IEEE Trans. VLSI Syst.

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“…The configuration proposed is based on a trans-impedance amplifier structure (TIA) 12,13,14 . As explained in the previous section, three main blocks compose the TIA.…”

Section: Circuit-level Designmentioning

confidence: 99%

“…By naming of Gm [dBΩ] the left-side term of equation(12) and under the assumption that the S21 value can be a good approximation of the voltage-to-voltage gain (Vout/Vin), the overall circuit trans-impedance AC gain can be evaluated as:…”

mentioning

confidence: 99%

<title>Band-pass transimpedance read-out circuit for UHF MEMS resonator applications</title>

Campanella

Uranga

Davis³

et al. 2005

SPIE Proceedings

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A detailed description of a read-out amplifier for high frequency MEMS resonators is done. Both read-out requirements and circuit architecture are presented. The architecture of the system is mainly based on three blocks: a trans-impedance amplifier, followed by a three-stage voltage-to-voltage amplifier, and finally by an output buffer amplifier. Physical design is based on AMS 0,35 µm technology. Also, simulation and fabrication results are presented and analyzed. Simulation results show an AC transimpedance gain of 70 dBΩ and a cut-off frequency of 400 MHz, for a band-pass bandwidth over 350 MHz. The fabricated amplifier has an input noise current spectral density of 11 pA/(Hz) 1/2 , a power dissipation of 200 mW, and occupies an active area of 600 µm * 450µm. Integration of read-out circuit with MEMS resonator has been designed and implemented, by properly connection of MEMS signals to the amplifier, in order to enable characterization of a set of MEMS resonators. Integration analysis will allow future extraction of electrical parameters of the resonator.

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“…Recently, a number of gigabit CMOS preamplifiers have been reported [2]- [9]. Among those, optoelectronic integrated circuits (OEICs) integrate silicon photodiodes with preamplifiers on the same substrate so that the input parasitic capacitance and inductance of the chip can be minimized [7]- [9].…”

mentioning

confidence: 99%

1.25-Gb/s Regulated Cascode CMOS Transimpedance Amplifier for Gigabit Ethernet Applications

Park

Yoo

2004

IEEE J. Solid-State Circuits

287

131

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2 Gbit/s transimpedance amplifier fabricated by 0.35 [micro sign]m CMOS technologies

Cited by 18 publications

References 5 publications

Systematic Simulation-Based Predictive Synthesis of Integrated Optical Interconnect

Systematic Simulation-Based Predictive Synthesis of Integrated Optical Interconnect

<title>Band-pass transimpedance read-out circuit for UHF MEMS resonator applications</title>

1.25-Gb/s Regulated Cascode CMOS Transimpedance Amplifier for Gigabit Ethernet Applications

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