2.8-Gb/s 176-mW byte-interleaved and 3.0-Gb/s 118-mW bit-interleaved 8:1 multiplexers with a 0.15-μm CMOS technology

Kurisu, M.; Kaneko, Miki; Suzaki, T.; Tanabe, A.; Togo, M.; Furukawa, Akira; Tamura, T.; Nakajima, Kanako

doi:10.1109/4.545826

Cited by 18 publications

(6 citation statements)

References 10 publications

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“…This proposed SerDes is also tested in a normal operation condition. By the comparison result with other works [5][6], we can confirm that our proposed SerDes is suitable for mobile display digital interface …”

Section: Resultssupporting

confidence: 81%

“…3 was designed using multiplexing method. The previous conventional method needs 8 clocks for one 8-bit data packet to make serialized data [5]. But our proposed serializer needs only four clocks by proposed serializer timing controller.…”

Section: Proposed Serializermentioning

confidence: 98%

“…Packet data in host are serialized with a cyclic redundancy check (CRC) to transfer data to client serially. To exchange parallel data using serial interface, the conventional SerDes methods have a trade-off between power consumption and speed limitation [5] [6]. If we reduce the number of clocks to serialize data using simple circuit, low power consumption and high speed can be achieved.…”

Section: Introductionmentioning

confidence: 99%

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A high resolution Serializer and Deserializer architecture for mobile image sensor module

2010

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This paper describes a new Serializer and Deserializer (SerDes) architecture for mobile camera serial interface CMOS image sensor module. This new SerDes architecture enables the effective transmission of digital packet with a timing controller. For the effective serializing and deserializing operations, we adopted the multiplexing technique with a Double Data Rate (DDR) process. By this technique, we can reduce the clock periods by half. The proposed SerDes structure with its transceiver was fabricated using 0.18um CMOS technology. This proposed circuit was verified by using a Mega pixel Mobile Display Digital Interface (MDDI) Image Sensor Module (ISM) at 500Mbps and also tested over this data rate. And this circuit shows low power consumption of 14mW at the supply voltage of 1.8 V.

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Section: Resultssupporting

confidence: 81%

Section: Proposed Serializermentioning

confidence: 98%

Section: Introductionmentioning

confidence: 99%

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A high resolution Serializer and Deserializer architecture for mobile image sensor module

2010

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“…1. The serial link operates at 2 Gb/s and is designed based on existing designs in [6] (3-Gb/s examples can be found in [7]). The 8:1 MUX schematic is depicted in Fig.…”

Section: A Case Study I: 2-gb/s Serial Linkmentioning

confidence: 99%

“…The 8:1 MUX schematic is depicted in Fig. 2, as proposed in [6]. The circuit generates a high-level pulse of duration 1/fout (fout: MUX's output frequency).…”

Section: A Case Study I: 2-gb/s Serial Linkmentioning

confidence: 99%

Design and feasibility of multi-Gb/s quasi-serial vertical interconnects based on TSVs for 3D ICs

Sun

Cevrero

Athanasopoulos

et al. 2010

2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip

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Abstract-This paper proposes a novel technique to exploit the high bandwidth offered by through silicon vias (TSVs). In the proposed approach, synchronous parallel 3D links are replaced by serialized links to save silicon area and increase yield. Detailed analysis conducted in 90 nm CMOS technology shows that the proposed 2-Gb/s/pin quasi-serial link requires approximately five times less area than its parallel bus equivalent at same data rate for a TSV diameter of 20 μm.

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Power efficient asynchronous multiplexer for X-ray sensors in medical imaging analog front-end electronics

Długosz¹,

Farine²,

Iniewski³

2011

Microelectronics Journal

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2.8-Gb/s 176-mW byte-interleaved and 3.0-Gb/s 118-mW bit-interleaved 8:1 multiplexers with a 0.15-μm CMOS technology

Cited by 18 publications

References 10 publications

A high resolution Serializer and Deserializer architecture for mobile image sensor module

A high resolution Serializer and Deserializer architecture for mobile image sensor module

Design and feasibility of multi-Gb/s quasi-serial vertical interconnects based on TSVs for 3D ICs

Power efficient asynchronous multiplexer for X-ray sensors in medical imaging analog front-end electronics

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