2.7 IBM z15: A 12-Core 5.2GHz Microprocessor

Berry, Christopher J.; Bell, Brian; Jatkowski, Adam; Surprise, Jesse; Isakson, John; Geva, Ofer; Deskin, Brian; Cichanowski, Mark; Hamid, Dina; Cavitt, Chris; Fredeman, Gregory; Saporito, Anthony; Mishra, Ashutosh; Buyuktosunoglu, Alper; Webel, Tobias; Lobo, Preetham; Parashurama, Pradeep Bhadravati; Bertran, Ramon; Chidambarrao, D.; Wolpert, David; Bruen, Brandon

doi:10.1109/isscc19947.2020.9063030

Cited by 18 publications

(8 citation statements)

References 4 publications

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Section: E Copa-gpu Enabling Technologiesmentioning

confidence: 99%

“…Cache Technology Projections: Large caches can be realized through high density Embedded DRAM (eDRAM) [9] or SRAM technologies [12], [21]. IBM recently implemented a 960MB cache on a 696mm 2 die using a 14nm eDRAM technology [9]. Graphcore's recently announced second-generation IPU [18] integrates 900MB of SRAM along with thousands of cores on a single 823 mm 2 die using TSMC's 7nm process.…”

Section: E Copa-gpu Enabling Technologiesmentioning

confidence: 99%

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GPU Domain Specialization via Composable On-Package Architecture

Fu¹,

Bolotin²,

Chatterjee³

et al. 2021

Preprint

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As GPUs scale their low precision matrix math throughput to boost deep learning (DL) performance, they upset the balance between math throughput and memory system capabilities. We demonstrate that converged GPU design trying to address diverging architectural requirements between FP32 (or larger) based HPC and FP16 (or smaller) based DL workloads results in sub-optimal configuration for either of the application domains. We argue that a Composable On-PAckage GPU (COPA-GPU) architecture to provide domain-specialized GPU products is the most practical solution to these diverging requirements. A COPA-GPU leverages multi-chip-module disaggregation to support maximal design reuse, along with memory system specialization per application domain. We show how a COPA-GPU enables DL-specialized products by modular augmentation of the baseline GPU architecture with up to 4× higher off-die bandwidth, 32× larger on-package cache, 2.3× higher DRAM bandwidth and capacity, while conveniently supporting scaled-down HPCoriented designs. This work explores the microarchitectural design necessary to enable composable GPUs and evaluates the benefits composability can provide to HPC, DL training, and DL inference. We show that when compared to a converged GPU design, a DL-optimized COPA-GPU featuring a combination of 16× larger cache capacity and 1.6× higher DRAM bandwidth scales per-GPU training and inference performance by 31% and 35% respectively and reduces the number of GPU instances by 50% in scale-out training scenarios.

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Section: E Copa-gpu Enabling Technologiesmentioning

confidence: 99%

Section: E Copa-gpu Enabling Technologiesmentioning

confidence: 99%

GPU Domain Specialization via Composable On-Package Architecture

Fu¹,

Bolotin²,

Chatterjee³

et al. 2021

Preprint

View full text Add to dashboard Cite

show abstract

“…Cloud computing in data-centers, internet-of-things devices, as well as applications related to mobile communication, automotive, and artificial intelligence drive the needs for increased data processing capabilities of modern microprocessors, which, today, operate at clock frequencies up to 5 GHz [1] and have tens of cores in their more advanced versions [1]- [3]. Increased computational power of microprocessors has been achieved by reducing the transistors' gate widths to below 22 nm in recent technology nodes, leading to breakdown voltages of less than 1 V. However, the performance increase comes at the cost of increased power consumption, exceeding 150 W per device [4], and is accompanied by high supply currents reaching values close to 100 A considering a typical package voltage of 1.8 V [5].…”

Section: Introductionmentioning

confidence: 99%

“…4(a) realize an Active Neutral Point Clamping (ANPC) circuit in order to avoid unbalanced voltages across the main power transistors during or after switching, to improve efficiency and reliability [27]. 1 The chip consists of four CMOS Half-Bridges (HBs) with ANPC, an open-loop logic circuitry to generate the switches' gate signals, and a configurable internal resistive load.…”

Section: Introductionmentioning

confidence: 99%

“…The frequency of the given clock signal is divided by 16, e.g., a clock signal with a frequency of 1.6 GHz at the ck in,hf -pad results in a switching frequency of 100 MHz. The switched output voltages are 1 According to [27], the ANPC topology is expected to achieve an increase of the efficiency by up to 2% at a switching frequency of 250 MHz. Fig.…”

Section: Introductionmentioning

confidence: 99%

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Electrical and Thermal Characterization of an Inductor-Based ANPC-Type Buck Converter in 14 nm CMOS Technology for Microprocessor Applications

Bezerra

Krismer

Kolar

et al. 2020

IEEE Open J. Power Electron.

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Integrated Voltage Regulators (IVRs) are attractive substitutes for conventional voltage regulators located on the motherboards, due to outstanding dynamic performances and superior power densities. IVRs operate with switching frequencies in the range of 100 MHz and are assembled in highly compact packages close to the microprocessor load. This paper presents a comprehensive characterization of a PCB-and inductorbased four-phase ANPC-type IVR that uses a Power Management IC (PMIC) implemented in a 14 nm CMOS technology node. The characterization is based on the results of electrical measurements, thermal inspections of the chip surface, and simulations, which enables the separation of the total losses into on-chip and off-chip loss components and the allocation of important loss components inside the chip. The investigated IVR achieves a maximum efficiency of 84.1 % at an output power of Pout = 640 mW and a switching frequency of fs = 50 MHz. The thermal measurements reveal that the maximum efficiency of the PMIC itself is between 88 % and 90 % at fs = 50 MHz and Pout ∈ [500 mW, 600 mW]; at Pout = 890 mW, a chip current density of 24.7 A/mm 2 is achieved. The findings in particular point out that the losses in the chip-internal interconnections, i.e., the conductors of the Power Distribution Network (PDN) and the twelve stacked metal layers below the PDN, have a substantial contribution to the total losses. Furthermore, the combination of Cadence post-layout simulations with impedance networks obtained from an appropriate software tool, e.g., FastHenry, is found to establish a suitable toolbox for estimating losses in IVRs.

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Emerging Memory Structures for VLSI Circuits

Garzón¹,

Yavits²,

Lanuzza³

et al. 2022

Wiley Encyclopedia of Electrical and Electronics Engineering

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Ever since the emergence of the electrical computer and the Von Neumann model, computer architects have adhered to a well‐structured hierarchy of memory solutions, clearly trading off performance and capacity with cost. The ubiquitous memory technologies, dominated by SRAM, DRAM, Flash, and magnetic hard disks, are each situated in a well‐defined location within this hierarchy. However, as processes have scaled into deep nanometer feature sizes and the demand for larger capacities and bandwidths increases, these traditional options face tough challenges and may be limited in their ability to continue to provide the new requirements. New technologies, such as phase change memory (PCM), magnetic RAM (MRAM), and resistive RAM (RRAM), have been researched and developed over the recent past in an attempt to meet these demands and replace some or all of the traditional technologies. In this article, the primary technologies are overviewed, including those that currently fill the memory hierarchy pyramid, the primary candidates to join or replace them in the near‐term, and a number of newer candidates that may arise as legitimate solutions in the farther term. In addition, an overview of the current state of processing within the emerging memory technologies is provided, as an attempt to break free of the traditional Von Neumann paradigm to overcome the energy and performance bottlenecks in modern systems.

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2.7 IBM z15: A 12-Core 5.2GHz Microprocessor

Cited by 18 publications

References 4 publications

GPU Domain Specialization via Composable On-Package Architecture

GPU Domain Specialization via Composable On-Package Architecture

Electrical and Thermal Characterization of an Inductor-Based ANPC-Type Buck Converter in 14 nm CMOS Technology for Microprocessor Applications

Emerging Memory Structures for VLSI Circuits

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