2.5GHz PLL with current matching charge-pump for 10Gbps transmitter design

Ko, Jaehong; Lee, Wookwan; Kim, Soo-Won

doi:10.1145/1057661.1057691

Cited by 2 publications

(1 citation statement)

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“…Even when these devices are in saturation the two currents show variation with the control voltage due to channel length modulation. Several designs [15,16] employ cascode mirrors in the charge pump to reduce this variation but this limits the operation speed of the charge pump and also consumes additional voltage headroom. This approach also fails to achieve current matching for the technologies having high values of lambda in which case cascade mirrors show marked dependence on the output drain voltage for all values of the output voltage.…”

Section: Charge Pump With Current Matchingmentioning

confidence: 99%

Half-Rate Duobinary Transmitter Architecture for Chip-to-Chip Interconnect Applications

Sharad

Mandal

2011

Analog Integr Circ Sig Process

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For a high speed duobinary transmitter clock frequency defines the transmission limit. A conventional duobinary transmitter needs a clock frequency equal to the data rate. In this work we propose a duobinary transmitter that uses a clock frequency half of the output data rate and hence achieves double the transmission rate for a given clock frequency as compared to a conventional duobinary transmitter. In the proposed transmitter the duobinary precoder is integrated into the last stage of a tree structured serializer to combine two NRZ data streams at half the transmission data rate. Two modes for the precoder have been incorporated into the design. The first mode is applicable for data transmission over copper whereas the second mode is suitable for wavelength division multiplexed optical transmission. A DLL based clock multiplier unit is employed to produce the high frequency clock with 50% duty cycle needed for the precoding operation. It incorporates a clock generation logic with integrated duty cycle control. A charge pump with dynamic current matching and a high resolution PFD are employed to reduce static phase error in locking and hence achieves improved jitter performance. A new delay cell along with automatic mode selection is proposed. To cover a wide range of data rate, the DLL is designed for a wide locking range and maintains almost 50% duty cycle. The design is implemented in 1.8-V, 0.18 lm Digital CMOS technology with an f T of 27 GHz. Simulations shows that, the duobinary transmitter circuit works up-to 10 Gb/s and consumes 60 mW of power.

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Section: Charge Pump With Current Matchingmentioning

confidence: 99%