2.5D and 3D technology challenges and test vehicle demonstrations

Knickerbocker, John; Andry, Paul; Colgan, E. G.; Dang, Bing; Dickson, T.O.; Gu, Xiaoxiong; Haymes, C.; Jahnes, C.; Liu, Y.; Maria, Joana; Polastre, R.; Tsang, C. K.; Turlapati, Lavanya; Webb, Bucknell C.; Wiggins, L. B.; Wright, S. L.

doi:10.1109/ectc.2012.6248968

Cited by 84 publications

(27 citation statements)

References 6 publications

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“…Thus, a designer needs to optimize the choices based on the application needs of routing and SI/PI requirements versus cost of processing. The next step is the physical implementation 19 of the 2.5D TSI. To do this, one needs accurate electrical models of the TSI (R, L, and C), and a PDK that is implemented on an EDA flow.…”

Section: Technology Planning and Design-executionmentioning

confidence: 99%

“…There are several underfill process flow options as well. [80][81][82][83] The most commonly used underfill methods for TSI assembly are non-conductive paste (NCP) and capillary underfill (CUF). The NCP is applied during flip chip attach and can only be used in conjunction with TCB assembly, while the CUF is used after the flip chip attach is done and can be used in conjunction with both TCB and mass reflow chip attach processes.…”

Section: B Tsi Package Assembly Process Flowmentioning

confidence: 99%

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Heterogeneous 2.5D integration on through silicon interposer

Zhang¹,

Lin²,

Wickramanayaka³

et al. 2015

Applied Physics Reviews

124

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Section: Technology Planning and Design-executionmentioning

confidence: 99%

Section: B Tsi Package Assembly Process Flowmentioning

confidence: 99%

Heterogeneous 2.5D integration on through silicon interposer

Zhang¹,

Lin²,

Wickramanayaka³

et al. 2015

Applied Physics Reviews

124

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“…The main difference between these two is whether a common silicon interposer, which is primarily utilized for signal distribution and pitch fanout, is used. Due to its simplicity in handling power density and distribution, and heat removal, 2.5D TSV is more attractive [8,9].…”

Section: Introductionmentioning

confidence: 99%

A new 2.5D TSV package assembly approach

Lü

Wang

Zhang

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

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Just in few years, three-dimensional (3D) packaging technologies have attracted much more attention. With emergence of through-silicon via (TSV) technology, siliconbased device integrations, the TSV's, have become the main stream of 3D packaging technologies. TSV's can be further classified as 2.5D and 3D TSV's. For 2.5D TSV package assembly, since multiple components involved, there are normally two assembly process approaches, i.e., from "Topto-Bottom" (TOB), or from "Bottom-to-Top (BOT). Each approach has its own pros and cons. From stress minimization aspect, TOB is more desirable. But from packaging assembly easiness viewpoint, BOT is more practical and thus has been mainly utilized. To overcome these dilemmas occurred in 2.5D TSV package assembly, a new assembly process approach, called new TOB (n-TOB), has been developed. Instead of bonding the chip onto the interposer, the n-TOB starts out with precisely bonding the interposer onto the chip with using a specially-designed eccentric-axis pickup tip which also effectively protects the flip chip C4 bumps on the interposer backside during bonding. Finite-element (FE) simulation and reliability tests were employed to assess the effectiveness and impact of this new assembly approach on 2.5D TSV packages. The assessment results show that n-TOB is feasible with at least the same performance in both package assembly and reliability.

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“…In response to standard packaging technologies, 2.5D passive silicon interposer technology is constantly catching attention with the window of opportunities it provides in the field of high wiring density, system partitioning, cost efficiency, low power and stress relief in fragile low-k dice [1,2].…”

Section: Introductionmentioning

confidence: 99%