2.3 60Gb/s NRZ and PAM4 transmitters for 400GbE in 65nm CMOS

Chiang, Po-Jui; Hung, Hao-Wei; Chu, Hsiang-Yun; Chen, Guan-Sing; Lee, Jri

doi:10.1109/isscc.2014.6757329

Cited by 30 publications

(14 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Short-distance applications such as backplane and chip-to-chip data links have similar approaches. Recent research also demonstrates the feasibility of realizing 48 60 Gb/s NRZ transmitters (TXs) in CMOS technologies [2], [3]. Meanwhile, transmitter equalization for electrical and optical channel loss has been shown at similar data rate [4], [5], and receivers (RXs) with decision-feedback equalizers (DFEs) have been announced as well [6], [7].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies

Lee

Chiang

Peng

et al. 2015

IEEE J. Solid-State Circuits

Self Cite

116

View full text Add to dashboard Cite

This paper presents two ultra-high-speed SerDes dedicated for PAM4 and NRZ data. The PAM4 TX incorporates an output driver with 3-tap FFE and adjustable weighting to deliver clean outputs at 4 levels, and the PAM4 RX employs a purely linear full-rate CDR and CTLE/1-tap DFE combination to recover and demultiplex the data. NRZ TX includes a tree-structure MUX with built-in PLL and phase aligner. NRZ RX adopts linear PD with special vernier technique to handle the 56 Gb/s input data. All chips have been verified in silicon with reasonable performance, providing prospective design examples for next-generation 400 GbE.Index Terms-Clock and data recovery (CDR), equalizer, highspeed serial link, NRZ, PAM4, phase-locked loop (PLL), SerDes, transceiver (TRX).

show abstract

Section: Introductionmentioning

confidence: 99%

“…The data swing is quite limited after equalization. Furthermore, the timing requirement for data and clock alignment in the transmitter becomes so stringent that a dynamic aligner becomes mandatory [3]. Finally, to the authors' best knowledge, no CMOS CDR circuit has ever been reported at such a high data rate.…”

Section: Introductionmentioning

confidence: 99%

Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies

Lee

Chiang

Peng

et al. 2015

IEEE J. Solid-State Circuits

Self Cite

116

View full text Add to dashboard Cite

show abstract

“…The fastest published SST drivers [3][4][5] accomplish low power consumption and low jitter, and operate in the data rate range adequate for the 28Gb/s standard generation (OIF-CEI-25G-LR, OIF-CEI-28G-VSR). To continue to exploit the high power efficiency and high voltage swing in the 50Gb/s generation applications and incoming standards (OIF-CEI-56G-VSR), SST drivers should be demonstrated that operate in the range of the fastest CML drivers [6,7,8] with sufficient output swing and return loss performance. In this paper we demonstrate a 2:1 multiplexer and a SST driver with such features by using a simple static CMOS design style without the passive components except in the termination, allowing for compact layout and high frequency of operation.…”

Section: Introductionmentioning

confidence: 99%

A DC-46Gb/s 2:1 multiplexer and source-series terminated driver in 20nm CMOS technology

Jiang

Parikh

Lionbarger

et al. 2014

2014 IEEE Asian Solid-State Circuits Conference (A-Sscc)

View full text Add to dashboard Cite

show abstract

“…Most previous standards for these networking applications use NRZ signaling. However, practical signal integrity constraints have led to a renewed interest in also supporting PAM4 for some applications and loss profiles [1][2]. Recently, several transmitters have been reported that operate between 28 and 60Gb/s using NRZ or PAM4 modulation exclusively [2][3][4].…”

mentioning

confidence: 99%

“…However, practical signal integrity constraints have led to a renewed interest in also supporting PAM4 for some applications and loss profiles [1][2]. Recently, several transmitters have been reported that operate between 28 and 60Gb/s using NRZ or PAM4 modulation exclusively [2][3][4]. However, high-speed SerDes building blocks that support both a wide frequency range and multiple forms of modulation provide more compatibility between components and avoid the development of multiple IPs.…”

mentioning

confidence: 99%

3.5 A 16-to-40Gb/s quarter-rate NRZ/PAM4 dual-mode transmitter in 14nm CMOS

Kim

Balankutty

Elshazly

et al. 2015

2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers

View full text Add to dashboard Cite

Intel, Hillsboro, OREmerging standards in wireline communication are defining a path to data-rates of 40Gb/s and beyond. Most previous standards for these networking applications use NRZ signaling. However, practical signal integrity constraints have led to a renewed interest in also supporting PAM4 for some applications and loss profiles [1][2]. Recently, several transmitters have been reported that operate between 28 and 60Gb/s using NRZ or PAM4 modulation exclusively [2][3][4]. However, high-speed SerDes building blocks that support both a wide frequency range and multiple forms of modulation provide more compatibility between components and avoid the development of multiple IPs. In addition, these blocks must continue to scale into the next-generation of CMOS process technologies to lower the cost by reducing area and power consumption. This paper presents a dual-mode transmitter (TX) implemented in 14nm CMOS that supports both NRZ and PAM4 modulations and operates from 16 to 40Gb/s. The TX incorporates a 4-tap NRZ FIR filter that is reconfigurable to drive PAM4 levels, quarter-rate clocking with a high-bandwidth 4:1 serializer, a duty-cycle and quadrature-error correction circuit with statistical phase error detection, and compact, multi-layer T-coils for pad capacitance (C pad ) reduction.The TX block diagram is presented in Fig. 3.5.1. An on-chip pattern generator sends 8b parallel data to a mode selector through a 16:8 MUX. The data is further serialized for 4-tap FFE in NRZ mode or split into four 2b bundles (MSB and LSB) in PAM4 mode, and fed into the output stage that consists of 36 segments to cover equalization/modulation as well as PVT variation of the termination resistance. Each segment contains a retimer, an equalization (EQ) selector, a single-ended-to-differential (S2D) converter, a 4:1 serializer, a pre-driver, and a source-series terminated (SST) driver with a shared resistor. Figure 3.5.1 also illustrates the output stage segmentation for both NRZ and PAM4 modes. In NRZ mode, the segments are divided into three parts: cursor/1 st pre-cursor, cursor/2 nd pre-cursor, and cursor/post-cursor which contain ¼, ¼, and ½ of the total number of segments, respectively. The configurability of the NRZ TX taps supports a wide range of channel profiles while minimizing the number of segments. In PAM4 mode, the MSB is fed to ⅔ of the segments and the LSB is fed to ⅓ of the segments to generate four different voltage levels without providing equalization. The TX maintains quarter-rate clocking and operates at half the symbol rate of NRZ mode to maintain the same data and clock paths.While half-rate and quarter-rate architectures ideally consume the same CV 2 f power, a quarter-rate serialization scheme can be an attractive solution at very high data-rates because it relaxes the speed and timing requirements in the serializer. Figure 3.5.2 (a) shows the 4:1 serializer using back-to-back pass-gates. Compared to a 2:1 serializer, the 4:1 serializer relaxes the critical timing path by 2UI that is set by t ck-q ...

show abstract

2.3 60Gb/s NRZ and PAM4 transmitters for 400GbE in 65nm CMOS

Cited by 30 publications

References 4 publications

Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies

Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies

A DC-46Gb/s 2:1 multiplexer and source-series terminated driver in 20nm CMOS technology

3.5 A 16-to-40Gb/s quarter-rate NRZ/PAM4 dual-mode transmitter in 14nm CMOS

Contact Info

Product

Resources

About