18k Channels single photon counting readout circuit for hybrid pixel detector

et al. 2016

IEEE Trans. Nucl. Sci.

Self Cite

This paper presents a readout integrated circuit called UFXC32k, designed for hybrid pixel semiconductor detectors used in X-ray imaging applications. The UFXC32k integrated circuit, designed in a CMOS 130 nm process, contains about 50 million transistors in the area of 9.64 mm × 20.15 mm. The core of the IC is a matrix of 128 × 256 square-shaped pixels of 75 µm pitch. Each pixel contains a charge sensitive amplifier, a shaper, two discriminators, and two 14-bit ripple counters. The analog front-end electronics allow processing of sensor signals of both polarities (holes and electrons). The UFXC32k chip is bumpbonded to a pixel silicon sensor and is fully characterized using X-ray radiation. The measured equivalent noise charge for the standard settings is equal to 123 e − rms (for the peaking time of 40 ns) and each pixel dissipates 26 µW. Thanks to the use of trim blocks working in each pixel independently, an effective offset spread calculated to the input is only 9 e − rms with a gain spread of 2%. The maximum count rate per pixel depends mainly on effective CSA feedback resistance. Dead time in the front end can be set as low as 85 ns. In the continuous readout mode, a user can select the number of bits read out from each pixel to optimize the UFXC32k frame rate, e.g., for a readout of 2 bits/pixel with 200 MHz clock, the frame rate is equal to 23 kHz.

Section: B High Count Rate Measurementsmentioning

confidence: 99%

32k Channel Readout IC for Single Photon Counting Pixel Detectors with Pitch, Dead Time of 85 ns, Offset Spread and 2% rms Gain Spread

Gryboś

Kmon

et al. 2016

IEEE Trans. Nucl. Sci.

Self Cite

“…The ROIC called "PXD18k" is designed at AGH University of Science and Technology and fabricated using UMC 180nm process. The detail of PXD18k is reported in the other paper [5]. The main feature of this ROIC is to have two discriminators so that it can set an energy window with low and high threshold.…”

Section: Hypix-3000mentioning

confidence: 99%

HyPix-3000 - a large area single-photon counting detector with two discriminator thresholds

2014 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC)

Gryboś

Szczygieł

et al. 2014

Self Cite

We report on the novel, single photon counting, large area X-Ray camera called HyPix-3000 for in-house XRD. Its active area is 77.5 mm x 38.5 mm (approx. 3000 mm2) and it consists of 298,375 square-shaped pixels of the 100 µm pitch, each of which contains charge sensitive amplifier, shaper and two discriminators followed by two independent 16-bit long counters. It can operate in ultra-high dynamic range mode having 31-bit long counter and in zero dead-time mode without missing any of the photons hitting the detector.Index Terms -X-ray detectors hybrid pixel detectors, single photon counting, X-ray imaging

“…More than that -those different modes of counters operation can be selected in each pixel individually. Beside the four different modes of counters operation, three modes of counters configuration is possible (set globally for the whole chip) in a similar way as in [9], namely:…”

Section: Working Modesmentioning

confidence: 99%

Testability features of a single photon counting hybrid pixel detector readout circuit with charge sharing elimination algorithm

2014 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC)

2014

Self Cite

The paper presents the specific testability features included in the design of a single photon counting hybrid pixel detector readout circuit built in the 40nm CMOS. The readout integrated circuit consists of a 18x24 pixel matrix with a pitch of 100 µm. Each pixel comprises of a charge sensitive amplifier, two shapers, two discriminators, eight comparators, tens of interpixel connections and a digital functionality allowing elimination of charge sharing effect using the C8P1 algorithm. Due to the high complexity of the chip, the extended testability features, allowing verification of single blocks and suitable for very small areas, are required. The paper presents the single pixel architecture with highlights of certain testability blocks, their description, area estimations and exemplary use cases.Keywords-hybrid pixel detectors, single photon counting readout chip, C8P1, charge sharing, testability I INTRODUCTIONNew designs of hybrid pixel detectors, working in the single photon counting mode, are more and more attractive as new, deep sub-micron technologies allow implementing more complex functionality in each channel maintaining small pixel's size at the same time. The smaller pixels size is wanted for many reasons, where the most desirable are:-smaller pixels size allow better spatial resolution, -more pixels per area allow operation with higher flux of X-Ray photons, However, while decreasing size of a single channel another limitations rise. One of the examples is the charge sharing effect, which occurs when a photon hits a detector in the area between pixels. Then, a charge cloud generated in this event spreads among more than one pixel. This effect is observed also for large pixels, but it is much more significant for the detectors containing smaller pixels and it causes the measurement uncertainty. Two of those uncertainties are important for the scope of this article, namely:-energy, as the fractioned charge shared between pixels does not reflect the total photon energy, -hit position, as the photon hit can be assigned to 2 (or more) neighboring pixels, Therefore, eliminating or compensating the described consequences of the charge sharing effect is required for further development of hybrid pixel detectors. Even though reducing this effect requires sufficient functionality inside each pixel and tens of interconnections between pixels, more and more groups are trying to solve this problem [1-5]. Our prototype application specific integrated circuit (ASIC) [6] contains the hardware solution of the C8P1 algorithm [1,4,7] challenging the charge sharing effect. Taking into account that the design of the C8P1 is very complicated (comparing to traditional single photon counting solutions) and the technology used (40 nm CMOS by TSMC) is new and not many reports on such solutions are available, a well thought over functionality is required for effective testing of the application specific integrated circuit (ASIC). The article presents the overall ASIC's architecture and C8P1 description in Section II and more...