2019 IEEE International Solid- State Circuits Conference - (ISSCC) 2019
DOI: 10.1109/isscc.2019.8662437
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18.3 An Auto-Zero Stabilized Voltage Buffer with a Quiet Chopping Scheme and Constant Input Current

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Cited by 7 publications
(12 citation statements)
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“…The main switches are driven by capacitively-coupled constant-VGS drive circuits (Fig. 4), which effectively add a fraction of a 1.8V clock signal to a buffered version of Vin [5]. The amplitude of the resulting clock signal Φ1,2_bo is determined by the ratio of the boosting capacitor (CB1-B2) to the parasitic capacitance to ground (CP1-P2).…”
Section: Input Current Trimming Schemementioning
confidence: 99%
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“…The main switches are driven by capacitively-coupled constant-VGS drive circuits (Fig. 4), which effectively add a fraction of a 1.8V clock signal to a buffered version of Vin [5]. The amplitude of the resulting clock signal Φ1,2_bo is determined by the ratio of the boosting capacitor (CB1-B2) to the parasitic capacitance to ground (CP1-P2).…”
Section: Input Current Trimming Schemementioning
confidence: 99%
“…Furthermore, it also causes output spikes, making it more difficult to interface such amplifiers with subsequent circuitry. Recently, an auto-zero (AZ) stabilized buffer has been proposed [4,5]. As shown in Fig.…”
Section: Introductionmentioning
confidence: 99%
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“…These methods are divided into two categories. One is the dynamic offset cancellation (DOC) technique, such as auto-zeroing [17]- [20], [30] and chopper [14], [21]- [23]. Auto-zeroing uses sampling-elimination technology to eliminate the offset voltage while the chopper uses high frequency modulation followed by bandwidth filter to decrease the offset voltage.…”
Section: Introductionmentioning
confidence: 99%