160Gb/s Serial Line Rates in a Monolithic Optoelectronic Multistage Interconnection Network

Abstract

Document VersionPublisher's PDF, also known as Version of Record (includes final page, issue and volume numbers)Please check the document version of this publication:• A submitted manuscript is the author's version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website.• The final author version and the galley proof are versions of the publication after peer review.• The final published version features the final layout of the paper including the volume, issue and page numbers. Link to publication General rightsCopyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights.• Users may download and print one copy of any publication from the public portal for the purpose of private study or research.• You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal ? Take down policyIf you believe that this document breaches copyright please contact us providing details, and we will remove access to the work immediately and investigate your claim. Download date: 13. May. 2018Abstract-We demonstrate very high line rate serial 160Gb/s data transmission through a semiconductor optical amplifier based multistage switching matrix. This represents both the leading edge in monolithic switching circuit complexity and the highest reported line rates through monolithically cascaded switching networks. Bit error rate studies are performed to show only modest levels of signal degradation. Power penalties of order 0.6dB and 1.2dB are observed for two stages and four stages respectively in the monolithic circuits at 160Gb/s per path.