16-Bit (4 × 4) Optical Random Access Memory (RAM) Bank

Pappas, Christos; Moschos, T.; Alexoudi, Theoni; Vagionas, Christos; Pleros, Nikos

doi:10.1109/jlt.2022.3205712

Cited by 6 publications

(6 citation statements)

References 46 publications

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“…For instance, the electronic connections between processor and memory units may limit the data throughput. Therefore, it is important to evaluate the Random Access Memory (RAM) and Video Random Access Memory (VRAM) implementations in terms of operational 2 of 18 speeds [GHz] [3]. The RAM device may be defined as the main computer memory used to store and process data, being placed at the computer's motherboard.…”

Section: Introductionmentioning

confidence: 99%

An Implementation of LASER Beam Welding Simulation on Graphics Processing Unit Using CUDA

Nascimento,

Magalhães,

Azevedo

et al. 2024

Computation

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The maximum number of parallel threads in traditional CFD solutions is limited by the Central Processing Unit (CPU) capacity, which is lower than the capabilities of a modern Graphics Processing Unit (GPU). In this context, the GPU allows for simultaneous processing of several parallel threads with double-precision floating-point formatting. The present study was focused on evaluating the advantages and drawbacks of implementing LASER Beam Welding (LBW) simulations using the CUDA platform. The performance of the developed code was compared to that of three top-rated commercial codes executed on the CPU. The unsteady three-dimensional heat conduction Partial Differential Equation (PDE) was discretized in space and time using the Finite Volume Method (FVM). The Volumetric Thermal Capacitor (VTC) approach was employed to model the melting-solidification. The GPU solutions were computed using a CUDA-C language in-house code, running on a Gigabyte Nvidia GeForce RTX™ 3090 video card and an MSI 4090 video card (both made in Hsinchu, Taiwan), each with 24 GB of memory. The commercial solutions were executed on an Intel® Core™ i9-12900KF CPU (made in Hillsboro, Oregon, United States of America) with a 3.6 GHz base clock and 16 cores. The results demonstrated that GPU and CPU processing achieve similar precision, but the GPU solution exhibited significantly faster speeds and greater power efficiency, resulting in speed-ups ranging from 75.6 to 1351.2 times compared to the CPU solutions. The in-house code also demonstrated optimized memory usage, with an average of 3.86 times less RAM utilization. Therefore, adopting parallelized algorithms run on GPU can lead to reduced CFD computational costs compared to traditional codes while maintaining high accuracy.

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Section: Introductionmentioning

confidence: 99%

An Implementation of LASER Beam Welding Simulation on Graphics Processing Unit Using CUDA

Nascimento,

Magalhães,

Azevedo

et al. 2024

Computation

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“…The idea of optical memory addressing with bit sequence, as well as building addressable storage is discussed in [20][21][22][23][24]. Some of these works are based on using Mach-Zehnder Interferometer (MZI) for both role of decoder and memory cell [20][21][22], where authors used SOA-MZI as memory cell. In this type of memory cell, Semiconductor Optical Amplifier (SOA) sits on one branch of MZI.…”

Section: Introductionmentioning

confidence: 99%

4 × 4 bit Programmable Optical Memory Array With Digital Addressing Using Micro-Ring Resonators

Nurgali,

Nakarmi,

Molardi

et al. 2024

IEEE Access

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The development of photonic integrated circuit (PIC) based computing systems requires efficient optical memory units, which can be challenging to implement due to the need for precise routing of optical signals. To address this challenge, we propose a 4x4 bit photonic non-volatile memory array system using micro ring resonators for fast and flexible memory addressing. The system uses phase change material (PCM) as a memory unit and implements wavelength division multiplexing (WDM) techniques to access memory cells through active and passive filtering by micro-ring resonators. Results show a system access speed of 30 Gbps with 50Mbps for erasing and 1.6Mbps for writing with accurate memory unit routing. This demonstration shows the potential for developing photonic non-volatile memory storage with reconfigurable memory addressing, which could facilitate the development of advanced PIC-based computing systems.

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“…Fetching data from the memory in current computing architectures is still carried out at a lower speed compared to the processing speed offered by the CPUs, a problem that has been already identified a few decades ago and is typically referred to as the "Memory Wall [1]. The efforts to overcome the speed limitations of electronic random-access memories (RAM) led to the introduction of a plethora of optical memory and optical RAM technologies during the last two decades [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20], with the main target being the transfer of the high-speed capabilities of photonic technologies into the memory segment. This aims at creating a seamless interface between the optical memory and the optical bus waveguide, enabling a transition into a data fetching and storing paradigm that can be performed exclusively in the optical domain.…”

Section: Introductionmentioning

confidence: 99%

“…In terms of memory capacity and integration density, the adoption of photonic crystal-based technology platforms allowed to reach ultra-small footprint values [6,7] and multi-bit capacity developments, allowing for an impressive 512-bit on-chip optical memory technology through the use of InP photonic crystal modules [8,9]. Finally, the migration towards highly functional optical memory blocks that can demarcate from simple multi-bit memory setups into addressable optical RAM banks and complete optical cache memories was initially proposed back in 2013 [10], but was only recently realized experimentally [11,12], designating an important milestone on the way to practical high-speed optical memory solutions that can support the whole chain of processes required within processor-memory transactions.…”

Section: Introductionmentioning

confidence: 99%

An all-passive Si₃N₄ optical row decoder circuit for addressable optical RAM memories

Simos,

Moschos,

Fotiadis

et al. 2023

J. Phys. Photonics

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In this work we experimentally demonstrate a Si 3 N 4 photonic integrated circuit which offers row decoding and RAM addressing functionalities. The passive integrated structure comprises a MRR-based wavelength filtering bank scheme in a 2 × 4 configuration, which reveals a suppression ratio in the range of 12–25 dB. The performance of the optical circuit has been evaluated in a system-level testbed, where successful addressing in one RAM row has been achieved. Error-free operation has been accomplished for all cases under study, with the whole row decoder system’s performance to offer a total power penalty of 2.5 dB.

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16-Bit (4 × 4) Optical Random Access Memory (RAM) Bank

Cited by 6 publications

References 46 publications

An Implementation of LASER Beam Welding Simulation on Graphics Processing Unit Using CUDA

An Implementation of LASER Beam Welding Simulation on Graphics Processing Unit Using CUDA

4 × 4 bit Programmable Optical Memory Array With Digital Addressing Using Micro-Ring Resonators

An all-passive Si₃N₄ optical row decoder circuit for addressable optical RAM memories

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16-Bit (4 × 4) Optical Random Access Memory (RAM) Bank

Cited by 6 publications

References 46 publications

An Implementation of LASER Beam Welding Simulation on Graphics Processing Unit Using CUDA

An Implementation of LASER Beam Welding Simulation on Graphics Processing Unit Using CUDA

4 × 4 bit Programmable Optical Memory Array With Digital Addressing Using Micro-Ring Resonators

An all-passive Si3N4 optical row decoder circuit for addressable optical RAM memories

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Product

Resources

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An all-passive Si₃N₄ optical row decoder circuit for addressable optical RAM memories