16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS

Mathew, Sanu; Satpathy, Sudhir; Anders, Mark; Kaul, Himanshu; Hsu, Steven; Agarwal, Amit; Chen, Gregory K.; Parker, Rachael J.; Krishnamurthy, Ram; De, Vivek

doi:10.1109/isscc.2014.6757433

Cited by 170 publications

(71 citation statements)

References 4 publications

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“…Since an ideal accuracy of 100% would require a large cost, typically, a low error rate such as an error rate of 10 −6 is used as the design target [9,10]. The solutions are discussed below.…”

Section: Related Literaturementioning

confidence: 99%

“…Mathew et al have proposed a solution based on Temporal Majority Voting (TMV) and dark bits evaluation [10]. They also employ burn-in and aging effects to improve the PUF.…”

Section: Circuit and Manufacturing Technology Solutionsmentioning

confidence: 99%

“…A simple way to reduce the error rate is using a Temporal Majority Voting scheme [10,23]. For example, a simple 4-bit counter based TMV counts from 0 to 15 and hence can be used as 15-way voting.…”

Section: Temporal Majority Votingmentioning

confidence: 99%

“…If the resultant value after 15 evaluations of the cell's response is greater than 8, then the final value is classified as 1, or else it can be classified as 0. The concept of TMV has been discussed extensively in previous works by Mathew et al and Xiao et al [10,23]. The mathematical model of the TMV is a binomial counting process and, hence, the reduction in error rate can be calculated analytically.…”

Section: Temporal Majority Votingmentioning

confidence: 99%

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On Improving Reliability of SRAM-Based Physically Unclonable Functions

Vijayakumar

Patil

Kundu

2017

JLPEA

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Physically unclonable functions (PUFs) have been touted for their inherent resistance to invasive attacks and low cost in providing a hardware root of trust for various security applications. SRAM PUFs in particular are popular in industry for key/ID generation. Due to intrinsic process variations, SRAM cells, ideally, tend to have the same start-up behavior. SRAM PUFs exploit this start-up behavior. Unfortunately, not all SRAM cells exhibit reliable start-up behavior due to noise susceptibility. Hence, design enhancements are needed for improving reliability. Some of the proposed enhancements in literature include fuzzy extraction, error-correcting codes and voting mechanisms. All enhancements involve a trade-off between area/power/performance overhead and PUF reliability. This paper presents a design enhancement technique for reliability that improves upon previous solutions. We present simulation results to quantify improvement in SRAM PUF reliability and efficiency. The proposed technique is shown to generate a 128-bit key in ≤0.2 µs at an area estimate of 4538 µm 2 with error rate as low as 10 −6 for intrinsic error probability of 15%.

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Section: Related Literaturementioning

confidence: 99%

“…Mathew et al have proposed a solution based on Temporal Majority Voting (TMV) and dark bits evaluation [10]. They also employ burn-in and aging effects to improve the PUF.…”

Section: Circuit and Manufacturing Technology Solutionsmentioning

confidence: 99%

Section: Temporal Majority Votingmentioning

confidence: 99%

Section: Temporal Majority Votingmentioning

confidence: 99%

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On Improving Reliability of SRAM-Based Physically Unclonable Functions

Vijayakumar

Patil

Kundu

2017

JLPEA

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“…Weak PUFs can either use special purpose variation-sensitive circuits or clever ways of detecting variations in existing circuits. Examples of custom-circuit weak PUFs include designs based on variations in drain currents [19], stabilization of cross-coupled devices [35], stabilization of cross-coupled devices in the presence of delay variations [22], and the skewed tendencies of sense amplifiers [3]. Examples of weak PUFs utilizing variations in existing circuitry include ones based on clock skew [14,37] and random flash memory latencies [28].…”

Section: Related Workmentioning

confidence: 99%

Bitline PUF: Building Native Challenge-Response PUF Capability into Any SRAM

Holcomb

2014

Advanced Information Systems Engineering

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Abstract. Physical Unclonable Functions (PUFs) are specialized circuits with applications including key generation and challenge-response authentication. PUF properties such as low cost and resistance to invasive attacks make PUFs well-suited to embedded devices. Yet, given how infrequently the specialized capabilities of a PUF may be needed, the silicon area dedicated to it is largely idle. This inefficient resource usage is at odds with the cost minimization objective of embedded devices. Motivated by this inefficiency, we propose the Bitline PUF -a novel PUF that uses modified wordline drivers together with SRAM circuitry to enable challenge-response authentication. The number of challenges that can be applied to the Bitline PUF grows exponentially with the number of SRAM rows, and these challenges can be applied at any time without power cycling. This paper presents in detail the workings of the Bitline PUF, and shows that it achieves high throughput, low latency, and uniqueness across instances. Circuit simulations indicate that the Bitline PUF responses have a nominal bit-error-rate (BER) of 0.023 at 1.2 V supply and 27• C, and that BER does not exceed 0.076 when supply voltage is varied from 1.1 V to 1.3 V, or when temperature is varied from 0• C to 80 • C. Because the Bitline PUF leverages existing SRAM circuitry, its area overhead is only a single flip-flop and two logic gates per row of SRAM. The combination of high performance and low cost makes the Bitline PUF a promising candidate for commercial adoption and future research.

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A physical unclonable function based on a 2‐transistor subthreshold voltage divider

Rose

Crupi

Lanuzza

et al. 2016

Circuit Theory & Apps

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In this paper, a compact circuit solution for silicon-based static physical unclonable functions (PUFs) is presented. The proposed solution exploits the variability of a simple voltage divider, implemented by two identical series-connected nMOSFETs in a commercial 65-nm CMOS process, to generate a random and stable nanokey. Both the transistors are biased in the subthreshold regime to enhance the output voltage dispersion and consequently the variability of the PUF response. The bit key generation is obtained by comparing the analog outputs of a pair of voltage dividers. Monte Carlo simulations on 10,000 samples have been performed to deduce the design guidelines for transistor sizing aimed at ensuring a high robustness of the PUF response against noise, supply voltage, and temperature variations. When compared with some state-of-the-art PUF designs, the proposed circuit solution proves to be a promising and competitive candidate for implementing analog and static PUFs featuring small area occupancy, low-power features, and high reliability. Figure 9. Temperature bit-flipping (bf T ) as a function of transistor channel (right) width (W) and (left) length (L) at V DD = 1V. [Colour figure can be viewed at wileyonlinelibrary.com]

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16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS

Cited by 170 publications

References 4 publications

On Improving Reliability of SRAM-Based Physically Unclonable Functions

On Improving Reliability of SRAM-Based Physically Unclonable Functions

Bitline PUF: Building Native Challenge-Response PUF Capability into Any SRAM

A physical unclonable function based on a 2‐transistor subthreshold voltage divider

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