16.1 A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7TOPS/W for Tiny AI Edge Devices

Xue, Cheng-Xin; Hung, Je-Min; Kao, Hui-Yao; Huang, Yen-Hsiang; Huang, Sheng-Po; Chang, Fu-Chun; Chen, Peng; Liu, Chun‐Jen; Jhang, Chuan-Jia; Su, Chun Jung; Khwa, Win-San; Lo, Chung-Chuan; Liu, Ren-Shuo; Hsieh, Chih-Cheng; Tang, Kea-Tiong; Chih, Yu-Der; Chang, Tsung-Yung Jonathan; Chang, Meng‐Fan

doi:10.1109/isscc42613.2021.9365769

Cited by 104 publications

(34 citation statements)

References 4 publications

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“…At an operation frequency of 1 GHz and a supply voltage of 0.8 V, the HERMES core shows a peak throughput of 1.008 TOPS at an efficiency of 10.5 TOPS/W, when running the MNIST-based experiment as described above. Compared to the (shown in Table I), the measured throughput density of 1.59 TOPS/mm 2 is significantly higher than recent non-volatile ReRAM-based designs [24], [45] and also slightly higher than recent SRAM + capacitor-based designs [44], when 8-bit input quantization is used. Only the SRAM-based design in [46] shows a better throughput density, given by its compact 8T SRAM unit-cell design employing push-rules and the advanced manufacturing node.…”

Section: System-level Performancementioning

confidence: 70%

HERMES-Core—A 1.59-TOPS/mm² PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

Khaddam-Aljameh

Stanisavljević

Mas

et al. 2022

IEEE J. Solid-State Circuits

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We present a 256 × 256 in-memory compute (IMC) core designed and fabricated in 14-nm CMOS technology with backend-integrated multi-level phase change memory (PCM). It comprises 256 linearized current-controlled oscillator (CCO)-based A/D converters (ADCs) at a compact 4-µm pitch and a local digital processing unit (LDPU) performing affine scaling and ReLU operations. A frequency-linearization technique for CCO is introduced, which increases the maximum Manuscript

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Section: System-level Performancementioning

confidence: 70%

HERMES-Core—A 1.59-TOPS/mm² PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

Khaddam-Aljameh

Stanisavljević

Mas

et al. 2022

IEEE J. Solid-State Circuits

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“…We also expect NVM scaling to further improve BioHD-DOT efficiency as it relies on minimal analog circuits. As NVMs are moving towards multi-bit technologies [79,80], BioHD-DOT is expected to provide higher density and efficiency. Robustness: Figure 10a compares BioHD robustness to noise in the memory devices.…”

Section: Biohd-pim Vs State-of-the-art Pimmentioning

confidence: 99%

BioHD

Zou

Chen

Poduval

et al. 2022

Proceedings of the 49th Annual International Symposium on Computer Architecture

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In this paper, we propose BioHD, a novel genomic sequence searching platform based on Hyper-Dimensional Computing (HDC) for hardware-friendly computation. BioHD transforms inherent sequential processes of genome matching to highly-parallelizable computation tasks. We exploit HDC memorization to encode and represent the genome sequences using high-dimensional vectors. Then, it combines the genome sequences to generate an HDC reference library. During the sequence searching, BioHD performs exact or approximate similarity check of an encoded query with the HDC reference library. Our framework simplifies the required sequence matching operations while introducing a statistical model to control the alignment quality. To get actual advantage from BioHD inherent robustness and parallelism, we design a processing in-memory (PIM) architecture with massive parallelism and compatible with the existing crossbar memory. Our PIM architecture supports all essential BioHD operations natively in memory with minimal modification on the array. We evaluate BioHD accuracy and efficiency on a wide range of genomics data, including COVID-19 databases. Our results indicate that PIM provides 102.8× and 116.1× (9.3× and 13.2×) speedup and energy efficiency compared to the state-of-theart pattern matching algorithm running on GeForce RTX 3060 Ti GPU (state-of-the-art PIM accelerator).

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“…Due to ReRAM device non-idealities, the sensing margin is normally a more critical design consideration for the target neural network accuracy. Hence, most ReRAM PIM works are based on current-mode sensing [34], [41]- [44].…”

Section: B Multiply-and-accumulate In Reram-based Pimmentioning

confidence: 99%

An Overview of Processing-in-Memory Circuits for Artificial Intelligence and Machine Learning

Kim

Xie

Chen

et al. 2022

IEEE J. Emerg. Sel. Topics Circuits Syst.

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Artificial intelligence (AI) and machine learning (ML) are revolutionizing many fields of study, such as visual recognition, natural language processing, autonomous vehicles, and prediction. Traditional von-Neumann computing architecture with separated processing elements and memory devices have been improving their computing performances rapidly with the scaling of process technology. However, in the era of AI and ML, data transfer between memory devices and processing elements becomes the bottleneck of the system. To address this data movement issue, memory-centric computing takes an approach of merging the memory devices with processing elements so that computations can be done in the same location without moving any data. Processing-In-Memory (PIM) has attracted research community's attention because it can improve the energy efficiency of memory-centric computing systems substantially by minimizing the data movement. Even though the benefits of PIM are well accepted, its limitations and challenges have not been investigated thoroughly. This paper presents a comprehensive investigation of state-of-the-art PIM research works based on various memory device types, such as static-random-access-memory (SRAM), dynamic-random-access-memory (DRAM), and resistive memory (ReRAM). We will present the overview of PIM designs in each memory type, covering from bit cells, circuits, and architecture. Then, a new software stack standard and its challenges for incorporating PIM with the conventional computing architecture will be discussed. Finally, we will discuss various future research directions in PIM for further reducing the data conversion overhead, improving test accuracy, and minimizing intra-memory data movement.

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16.1 A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7TOPS/W for Tiny AI Edge Devices

Cited by 104 publications

References 4 publications

HERMES-Core—A 1.59-TOPS/mm² PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

HERMES-Core—A 1.59-TOPS/mm² PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

BioHD

An Overview of Processing-in-Memory Circuits for Artificial Intelligence and Machine Learning

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16.1 A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7TOPS/W for Tiny AI Edge Devices

Cited by 104 publications

References 4 publications

HERMES-Core—A 1.59-TOPS/mm2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

HERMES-Core—A 1.59-TOPS/mm2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

BioHD

An Overview of Processing-in-Memory Circuits for Artificial Intelligence and Machine Learning

Contact Info

Product

Resources

About

HERMES-Core—A 1.59-TOPS/mm² PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

HERMES-Core—A 1.59-TOPS/mm² PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs