15.3 A 351TOPS/W and 372.4GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning Applications

An SRAM-Based Multibit In-Memory Matrix-Vector Multiplier With a Precision That Scales Linearly in Area, Time, and Power

“…To adequately reflect the additional computational complexity tackled by multibit accelerators, the respective quantization of weight n w and input n x can be factored in, similar to the approach taken in [19], yielding precision scaled TOP/s and TOP/s/W. This is shown in Table III, where recent implementations of analog in-memory MAC-operation accelerators using SRAM combined with capacitors [17], [18], [30], [31] are compared with the presented work.…”

“…For example, a scheme that could scale in terms of weight and input bits is demonstrated in [30]. In this article, a specific implementation for 4-bit inputs is presented.…”

“…Finally, note that the overall area overhead introduced for enabling the IMC capabilities remains manageable since, similar to [19], the standard SRAM-macrointernals remained unmodified, and exclusively, pitch-matched components are added to the periphery. In summary, the system described in [30] delivers high energy and area efficiency for the selected 4-bit input and weight quantization with the relatively low throughput being the only downside. This architecture might match well with the common requirements for IoT and edge applications.…”

An Energy-Efficient Time-Domain Analog CMOS BinaryConnect Neural Network Processor Based on a Pulse-Width Modulation Approach

“…The energy efficiency of 300 TOPS/W in this work is six times as high as that of a state-of-the-art in-memory-computing AI processor implementing the same BinaryConnect model, while the VLSI technology node used in this work is fourgeneration older than that in the AI processor [25], as shown in Table 2. One of the latest AI processors fabricated using a 7 nm-node VLSI technology [18] is also included in Table 2. It is noted that, even compared with this processor, the energy efficiency of our present processor is comparable.…”

“…As an implementation approach other than digital processors, the use of analog operation in CMOS VLSI circuits is a promising method for achieving extremely low-power consumption for such calculation tasks [11]- [14]. In particular, in-memory computing (IMC) approaches, which achieve weighted-sum calculation utilizing the memory circuit, such as static-random-access memory (SRAM), have been popular since around 2016 [15]- [18].…”