14-nm FinFET 1.5 Mb Embedded High-K Charge Trap Transistor One Time Programmable Memory Using Differential Current Sensing

Hunt-Schroeder, Eric; Anand, D.; Fifield, J.A.; Roberge, Michael; Pontius, D.; Jacunski, Mark; Batson, Kevin; Deming, Matthew; Khan, Faraz A.; Moy, D.; Cestero, Alberto; Katz, Robert; Chbili, Z.; Banghart, Edmund; Liu, Jiang; Jayaraman, Balaji; Tummuru, Rajesh R.; Raghavan, Ramesh; Mishra, Amit Kumar; Robson, N.; Kirihata, T.

doi:10.1109/lssc.2019.2899519

Cited by 5 publications

(2 citation statements)

References 8 publications

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“…The model explicitly describes and decouples the electric-field and self-heating temperature dependencies of charge trapping in CTTs, which is also applicable to charge trapping in HKMG devices in general. A 14 nm FinFET CTT based one-time programmable memory (OTPM) product has already been deployed: circuit design aspects, including a Differential Current Sense Amplifier (DCSA) used during reads and for margining the V T shifts during programming, are discussed in [10]. While only programming related aspects of CTTs are discussed in this letter, CTTs can also be employed as multi-time programmable memory (MTPM) elements, which would of course require erasing the programmed devices efficiently.…”

Section: Discussionmentioning

confidence: 99%

Design Optimization and Modeling of Charge Trap Transistors (CTTs) in 14 nm FinFET Technologies

Khan

Han

Moy

et al. 2019

IEEE Electron Device Lett.

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The Charge Trap Transistor (CTT) technology is an emerging memory solution that turns as-fabricated high-k /metal gate (HKMG) logic transistors into secure, embedded non-volatile memory (eNVM) elements with excellent data retention and operation capability at military grade temperatures. In other words, the CTTs offer a completely process-free and mask-free eNVM solution for advanced HKMG CMOS technology nodes. In this letter, bitcell design to enhance programming efficiency and modeling of the charge trapping behavior of CTTs in 14 nm FinFET technology is discussed. Index Terms-Charge Trap Transistor (CTT), embedded non-volatile memory (eNVM), process-free, mask-free, high-k /metal gate (HKMG), CMOS. I. INTRODUCTION W HILE need for on-chip non-volatile memory in VLSI technologies continues to grow rapidly, the options have been limited due to integration and scaling challenges as well as operational voltage incompatibilities. eFUSE and anti-fuse [1] technologies require high voltages which are logic incompatible and also face scaling challenges. Other memory technologies like MONOS (metal-oxide-nitride-oxidesilicon) [2] and MRAM (magnetoresistive random access memory) [3] require additional complex processes and masks. Unlike the aforementioned memories, CTTs offer an embedded non-volatile memory (eNVM) solution that requires absolutely no additional processes or masks, operates at logiccompatible voltages (∼2V maximum), and is scalable. Chip configuration, repair at wafer and module test and in the field, firmware, and performance tailoring are some applications of CTT eNVM. CTTs also find their applications in security enhancements such as chip ID, authentication, and encryption key storage.

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Section: Discussionmentioning

confidence: 99%

Design Optimization and Modeling of Charge Trap Transistors (CTTs) in 14 nm FinFET Technologies

Khan

Han

Moy

et al. 2019

IEEE Electron Device Lett.

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“…In this case-temperature management-sensors are needed to measure these Nano effects. Temperature has a significant effect on the system performance and the expected life of electronic products especially with the increasingly dense circuitry in a single chip [20,21]. The remaining part of this paper is organized as follows: the next section presents an overview about SiNWT structure, which followed by the adopted methods for this work.…”

Section: Introductionmentioning

confidence: 99%

Characterization of silicon nanowire transistor

et al. 2019

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This paper analyses the temperature sensitivity of Silicon Nanowire Transistor (SiNWT) depends on the diameter (D.ch) of channel. In addition, it also investigates the possibility of utilizing SiNWT as a Nano-temperature sensor. The MuGFET simulation tool has been utilized to conduct a comprehensive simulation to evaluate both electrical and temperature characteristics of SiNWT. Current-voltage characteristics with different values of temperature and with a varying diameter of the Nano wire channel (D.ch = 80, 40, 20 and 10 nm), were simulated. Diode operating mode connection of the transistor is suggested for measuring the temperature sensitivity of SiNWT. As simulation results demonstrated, the best temperature sensitivity was occurred at lower temperature with increasing the channel diameter. We also illustrate the impact of varying temperature and channel diameter on electrical characteristics of SiNWT including, Subthreshold Swing (SS), Threshold voltage (V.th), and Drain-induced barrier lowering (DIBL), which were proportionally increased with the operating temperature.

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Pre-Amplifier Based Entropy Source with Stable Output for use in a Physical Unclonable Function

Hunt-Schroeder

Xia

2021

2021 IEEE Microelectronics Design &Amp; Test Symposium (MDTS)

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14-nm FinFET 1.5 Mb Embedded High-K Charge Trap Transistor One Time Programmable Memory Using Differential Current Sensing

Cited by 5 publications

References 8 publications

Design Optimization and Modeling of Charge Trap Transistors (CTTs) in 14 nm FinFET Technologies

Design Optimization and Modeling of Charge Trap Transistors (CTTs) in 14 nm FinFET Technologies

Characterization of silicon nanowire transistor

Pre-Amplifier Based Entropy Source with Stable Output for use in a Physical Unclonable Function

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