13.1 A 1Tb 4b/cell NAND Flash Memory with t<sub>PROG</sub>=2ms, t<sub>R</sub>=110µs and 1.2Gb/s High-Speed IO Rate

Kim, Doo-Hyun; Kim, Hyung-Gon; Sung-Won, Yun; Song, Young-Jae; Kim, Jisu; Joe, Sung-Min; Kang, Kyung-Hwa; Jang, Joonsuc; Yoon, Hyun-Jun; Lee, Kanabin; Kim, Minseok; Kwon, Joonsoo; Jo, Jonghoo; Park, Se-Hwan; Park, Jiyoon; Cho, Jisoo; Park, Sohyun; Kım, Garam; Bang, Jinbae; Kim, Heejin; Park, Jong-Eun; Lee, Deokwoo; Lee, Seonyong; Jang, Hwajun; Lee, Han-Jun; Shin, Dong‐Hui; Park, Jungmin; Kim, Jungkwan; Kim, Jongmin; Jang, Kichang; Park, Ii Han; Moon, Seuna Hyun; Choi, Minsuk; Kwak, Pansuk; Park, Joo-Yona; Choi, Yong‐Sang; Kim, Sanglok; Lee, Seungjae; Kang, Dong‐Ku; Lim, Jeong-Don; Byeon, Dae–Seok; Song, Ki–Whan; Choi, Jung-Hwan; Hwang, Sang Joon; Jeong, Jin Hee

doi:10.1109/isscc19947.2020.9063053

Cited by 21 publications

(23 citation statements)

References 5 publications

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“…Among the several architectural solutions for 3D storage [39][40][41][42][43][44][45][46], the one employing vertical-channel strings crossed by a set of planar wordlines has become the most effective one [47][48][49][50], and is the focus of this section. Here we will briefly describe the main features of such an array, namely its organization and cell structure, referring to previous works for further details [51].…”

Section: Array and Cell Structurementioning

confidence: 99%

Random Telegraph Noise in 3D NAND Flash Memories

et al. 2021

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In this paper, we review the phenomenology of random telegraph noise (RTN) in 3D NAND Flash arrays. The main features of such arrays resulting from their mainstream integration scheme are first discussed, pointing out the relevant role played by the polycrystalline nature of the string silicon channels on current transport. Starting from that, experimental data for RTN in 3D arrays are presented and explained via theoretical and simulation models. The attention is drawn, in particular, to the changes in the RTN dependences on the array working conditions that resulted from the transition from planar to 3D architectures. Such changes are explained by considering the impact of highly-defective grain boundaries on percolative current transport in cell channels in combination with the localized nature of the RTN traps.

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Section: Array and Cell Structurementioning

confidence: 99%

Random Telegraph Noise in 3D NAND Flash Memories

et al. 2021

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“…To realize the NIR-emitting Ir(III) complexes, the strategy of using the cyclometalated ligands with the extensively conjugated rings was used (Qiao et al, 2009). Even though the emission wavelengths are obviously red-shifted, the 3 MLCT contributions at the excited state manifolds of these Ir(III) complexes decreased and the increased p-p interactions between neighboring entities may cause a strong triplet-triplet annihilation (TTA) (Kim et al, 2020), resulting in the undesired decay to the ground states through nonradiative decays. While the use of the rigid and unitary cyclometalated ligands in the Ir(III) phosphors was recently studied, this method can restrict the intramolecular motion and was demonstrated to improve PLQYs of the designed Ir(III) complexes (You et al, 2020a); however, the intricate chemical structures and multistep synthesis steps may limit its practical application.…”

Section: Introductionmentioning

confidence: 99%

Iridium(III) complexes with 1-phenylisoquinoline-4-carbonitrile units for efficient NIR organic light-emitting diodes

Zhang

Chen

et al. 2021

iScience

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Summary Achieving the high external quantum efficiency (EQE) of near-infrared (NIR) emission in iridium(III) complexes still remains a challenge owing to their unsteady excited states which easily decay to the ground states through the nonradiative pathways. Herein, three Ir(III) phosphors in which the cyclometalated ligand 1-phenylisoquinoline-4-carbonitrile (piq-CN) is functionalized with the cyano, tert- butyl, and dimethyl groups are developed (CN-CNIr, Bu-CNIr, and DM-CNIr, respectively). Three simple synthetic steps can afford this class of deep red to NIR Ir(III) emitters. The organic light-emitting diodes (OLEDs) based on Bu-CNIr and DM-CNIr attain the maximum EQEs of 7.1% and 7.2% with the emission peaks at 695 and 714 nm, respectively. This strategy using substituted piq-CN derivatives as the cyclometalated ligands can offer an effective approach to promote the radiative rate of NIR-emitting Ir(III) materials. An insight into how the electron-withdrawing and electron-donating substituents on ligands influence the optoelectronic properties of their Ir(III) complexes is also provided.

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“…In addition, MLC technology significantly reduces the margin between different V TH levels used to store multiple bits in a single flash cell. Consequently, the V TH level of a 3D NAND flash cell with advanced MLC techniques (e.g., triple-level cell (TLC) [6,37] or quad-level cell (QLC) [32,44]) can quickly shift beyond the read-reference voltage V REF (i.e., the voltage used to distinguish between cell V TH levels) after programming, which results in an error when reading the cell.…”

Section: Introductionmentioning

confidence: 99%

Reducing solid-state drive read latency by optimizing read-retry

Park

Kim

Chun

et al. 2021

Proceedings of the 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

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3D NAND flash memory with advanced multi-level cell techniques provides high storage density, but suffers from significant performance degradation due to a large number of read-retry operations. Although the read-retry mechanism is essential to ensuring the reliability of modern NAND flash memory, it can significantly increase the read latency of an SSD by introducing multiple retry steps that read the target page again with adjusted read-reference voltage values. Through a detailed analysis of the read mechanism and rigorous characterization of 160 real 3D NAND flash memory chips, we find new opportunities to reduce the read-retry latency by exploiting two advanced features widely adopted in modern NAND flash-based SSDs: 1) the CACHE READ command and 2) strong ECC engine. First, we can reduce the read-retry latency using the advanced CACHE READ command that allows a NAND flash chip to perform consecutive reads in a pipelined manner. Second, there exists a large ECC-capability margin in the final retry step that can be used for reducing the chip-level read latency. Based on our new findings, we develop two new techniques that effectively reduce the read-retry latency: 1) Pipelined Read-Retry (PR 2 ) and 2) Adaptive Read-Retry (AR 2 ). PR 2 reduces the latency of a read-retry operation by pipelining consecutive retry steps using the CACHE READ command. AR 2 shortens the latency of each retry step by dynamically reducing the chip-level read latency depending on the current operating conditions that determine the ECC-capability margin. Our evaluation using twelve real-world workloads shows that our proposal improves SSD response time by up to 31.5% (17% on average) over a state-of-the-art baseline with only small changes to the SSD controller. CCS CONCEPTS• Hardware → External storage.

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13.1 A 1Tb 4b/cell NAND Flash Memory with t_PROG=2ms, t_R=110µs and 1.2Gb/s High-Speed IO Rate

Cited by 21 publications

References 5 publications

Random Telegraph Noise in 3D NAND Flash Memories

Random Telegraph Noise in 3D NAND Flash Memories

Iridium(III) complexes with 1-phenylisoquinoline-4-carbonitrile units for efficient NIR organic light-emitting diodes

Reducing solid-state drive read latency by optimizing read-retry

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13.1 A 1Tb 4b/cell NAND Flash Memory with tPROG=2ms, tR=110µs and 1.2Gb/s High-Speed IO Rate

Cited by 21 publications

References 5 publications

Random Telegraph Noise in 3D NAND Flash Memories

Random Telegraph Noise in 3D NAND Flash Memories

Iridium(III) complexes with 1-phenylisoquinoline-4-carbonitrile units for efficient NIR organic light-emitting diodes

Reducing solid-state drive read latency by optimizing read-retry

Contact Info

Product

Resources

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13.1 A 1Tb 4b/cell NAND Flash Memory with t_PROG=2ms, t_R=110µs and 1.2Gb/s High-Speed IO Rate