128-bit multicomparator

Abstract

A 128-bit multicomparator was designed to perform the search-sort function on arbitrary length data strings. Devices can be cascaded for longer block lengths or paralleled for bit-parallel, wordseriai applications. The circuit utilizes a 3-phase static-dynamic shift register cell for data handling and a unique gated EXCLUSIVE-NORcircuit to accomplish the compare function. The compare operation is performed bit parallel between a "data" register and a "key" register with a third "mask" register containing DON'T CARE bits that disable the comparator. The multicomparator was fabricated using p-channel silicongate metal-oxide-semiconductor (MOS) technolo~on a 107 X 150 mil chip containing 3350 devices. With transistor-transistor logic (TTL) input, data rates in excess of 2 MHr have been attained. The average power dissipation was 250 mW in the dynamic mode and 300 mW in the static mode.

The Burrows-Wheeler Transform: Data Compression, Suffix Arrays, and Pattern Matching

“…Each cell at every clock cycle encounters two characters entering the cell, compares them for match or mismatch, and accumulates a result that is sent to the output along with the last character of the text. The method does not handle any FLDC or VLDC characters, and this is also true for parallel comparatorbased pattern matching proposed earlier by Mead et al (1976) and .…”