2021 Twelfth International Conference on Ubiquitous and Future Networks (ICUFN) 2021
DOI: 10.1109/icufn49451.2021.9528534
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12-Bit 5 MS/s SAR ADC with Hybrid Type DAC for BLE Applications

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Cited by 2 publications
(1 citation statement)
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“…When designing the DAC circuit, considering the layout area of the DAC in the design, many researchers opt to reduce the DAC layout area as much as possible by using a bridged capacitor approach. However, in this paper, a capacitor-resistor-based structure is employed to effectively reduce the DAC layout area [4][5]. For the comparator circuit, this paper utilizes a structure that combines a cascade of three-stage pre-amplifiers with one latch.…”
Section: Introductionmentioning
confidence: 99%
“…When designing the DAC circuit, considering the layout area of the DAC in the design, many researchers opt to reduce the DAC layout area as much as possible by using a bridged capacitor approach. However, in this paper, a capacitor-resistor-based structure is employed to effectively reduce the DAC layout area [4][5]. For the comparator circuit, this paper utilizes a structure that combines a cascade of three-stage pre-amplifiers with one latch.…”
Section: Introductionmentioning
confidence: 99%