This paper presents the design of a 12-bit 4 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) based on the 40nm CMOS process. The internal structure of the ADC employs an "8MSB+4LSB" hybrid capacitive-resistive structure in the digital-to-analog converter (DAC) design to reduce layout area. The comparator circuit utilizes a dynamic comparator structure consisting of a cascade of three pre-amplifiers and a single latch, with output offset storage used to minimize comparator offset voltage. The layout design is symmetric to enhance device matching. In post-simulation under the conditions of 1.1 V analog voltage, a 941.40625 KHz input sine wave signal, and a 4 MHz sampling clock, the SAR ADC achieved an effective number of bits (ENOB) is 11.88 bits, a signal to noise and distortion ratio (SNDR) is 73.2941 dB, a spurious-free dynamic range (SFDR) is 89.4 dB, a power consumption is 1.18 mW, and a figure-of-merit (FoM) is 168.6 dB.