10Gb/s inverter based cascode transimpedance amplifier in 40nm CMOS technology

Atef, Mohamed; Chen, Hong; Zimmermann, Horst

doi:10.1109/ddecs.2013.6549791

Cited by 17 publications

(22 citation statements)

References 11 publications

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“…The junction capacitance C p of the 3D integrated (mounted) photodiode is expected to be 4 fF, capacitance C pad of IWC pads is 10 fF and IWC capacitance C IWC is less than 1 fF. The calculated sensitivity of the receiver with mounted photodiode falls in the range of the typical sensitivities of the state of the art receivers [5,6]. The hybrid integration of the photonic and electrical chip is yet to be done, therefore the measurement results for 3D-integrated OEIC are not available.…”

Section: A Simulated Results -Mounted Photodiodementioning

confidence: 94%

Optical receivers in 0.35 μm BiCMOS for heterogeneous 3D integration

Milovančev

Brandl

Vokić

et al. 2016

2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems (DDECS)

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Developing paradigm in high speed communication device is heterogeneous 3D integration of electronic componentsdesigned on standard silicon wafers -and photonics, optimized in different processes. This paper shows the advantages of 3D integration and presents the measured results of two receivers fabricated in 0.35 μm SiGe BiCMOS technology. The first is a 10 Gbit/s regulated cascode (RGC) based receiver for optical communications and the second is a 200 Mbit/s TIA for monitoring the operating point of the photonic ring modulator.

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Section: A Simulated Results -Mounted Photodiodementioning

confidence: 94%

Optical receivers in 0.35 μm BiCMOS for heterogeneous 3D integration

Milovančev

Brandl

Vokić

et al. 2016

2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems (DDECS)

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“…21 This inductor degeneration also improves the FIGURE 3 The circuit schematic of the differential form of the CMOS inverter-based amplifier with current-source biasing. Other modifications to the conventional inverter-based amplifier can be found in Atef et al, Atef, and Ni et al [33][34][35][36] The optimization of this amplifier topology was investigated quantitatively in Park et al 37 The open-loop configuration has high input and output impedances, thus it is suitable for operation as a transconductance amplifier. Increasing the gain of the configuration of Figure 4B by adopting a large-valued R F causes the input resistance to rise, thus degrading both the bandwidth, 25 the stability, 26 and the input matching.…”

Section: Previous Workmentioning

confidence: 99%

“…In Atef and Zimmermann, 32 a common-drain feedback was instead used. Other modifications to the conventional inverter-based amplifier can be found in Atef et al, Atef, and Ni et al [33][34][35][36] The optimization of this amplifier topology was investigated quantitatively in Park et al 37 The open-loop configuration has high input and output impedances, thus it is suitable for operation as a transconductance amplifier. 38 The resistive-feedback configuration, on the other hand, has both low input and output impedances, thus it is suitable for operation as a transimpedance amplifier.…”

Section: Previous Workmentioning

confidence: 99%

Design of the CMOS inverter‐based amplifier: A quantitative approach

Sharroush

2019

Circuit Theory & Apps

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The CMOS inverter can be used as an amplifier if properly biased in the transition region of its voltage-transfer characteristics (VTC). In this paper, the design of this amplifier is investigated with its merits and demerits illustrated and with the various trade-offs involved in its design discussed. Specifically, the following performance metrics are discussed quantitatively: gain, area, linearity, maximum allowable swing, bandwidth, stability, noise factor, impedance matching, and slew rate. Also, the effect of process, voltage, and temperature (PVT) variations are investigated. The optimum number of stages corresponding to the minimum area required for achieving a certain voltage gain is determined. The results obtained from the quantitative analysis and the simulation are discussed.

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“…This study is compared with other CMOS technologies under the same operating conditions. 2,3 Inductorless cascade configuration TIAs for optical communication systems are realized in 0.35-μm CMOS technology with possible transmission bit rate of 3.125 Gb/s. The measurements show the TIA gain of 54.2 dBΩ, 3-dB bandwidth of 2.31 GHz, power consumption of 58.08 mW with supply voltage of 3.3 V, and input reference noise current spectral density which reached 18.8 pA/Hz 1/2 .…”

Section: Related Workmentioning

confidence: 99%

Best candidate integrated technology for low‐noise, high‐speed, and wide bandwidth‐based transimpedance amplifiers in optical computing systems and optical fiber applications

Rashed

Tabbour

2018

Int J Communication

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Summary This paper presents the best candidate integrated technology for achieving low‐noise, high‐speed, and wide bandwidth transimpedance amplifiers in optical computing and communication systems. Different complementary metal oxide semiconductor (CMOS) technology sizes are employed in addition to high electron mobility transistor (HEMT), bipolar CMOS (BiCMOS), and gallium arsenide technologies‐based transimpedance amplifiers to achieve high‐speed capability with low noise. These different technologies are applied on two proposed models to test the performance parameters. Maximum output signal voltage, maximum RF power spectrum, received output power, maximum Q‐factor, and minimum bit error rate are the tradeoff parameters for two proposed models at high transmission bit rates up to 400 Gb/s. It is observed that 600‐nm CMOS technology has presented the best candidate to deal with high transmission bit rates because of its superior performances in either the first proposed model or the second proposed model compared with other technologies under study. Figure of merit is applied on two proposed models and previous works to show the high‐speed performance operation of transimpedance amplifiers in our proposed models. The signal is tested before and after transimpedance amplifiers in different technologies.

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10Gb/s inverter based cascode transimpedance amplifier in 40nm CMOS technology

Cited by 17 publications

References 11 publications

Optical receivers in 0.35 μm BiCMOS for heterogeneous 3D integration

Optical receivers in 0.35 μm BiCMOS for heterogeneous 3D integration

Design of the CMOS inverter‐based amplifier: A quantitative approach

Best candidate integrated technology for low‐noise, high‐speed, and wide bandwidth‐based transimpedance amplifiers in optical computing systems and optical fiber applications

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