100-nm generation contact patterning by low temperature 193-nm resist reflow process

Driessche, Veerle Van; Lucas, Kevin; Roey, Frieda Van; Grozev, Grozdan; Tzviatkov, Plamen

doi:10.1117/12.474204

Cited by 2 publications

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“…Decreases in LER and LWR show the same phenomenon as well as the shrinkage of contact holes, as observed in previous studies. 9,10,12,14) Thus, LER and LWR could decrease to $2 nm. When the roughness of the resist decreases with RRP, the thickness of the resist also decreases and the resist width expands.…”

Section: Discussionmentioning

confidence: 98%

“…13) To improve the performance of RRP, a binary mask and an attenuated phase-shift mask are used. 14) The molecular weight, blocking ratio of the resin, cross-linker amount, and solvent type were varied to investigate the effects of chemical characteristics on the contact hole pattern. 15) RRP is applied not only to the contact hole pattern but also to the microlenses.…”

Section: Introductionmentioning

confidence: 99%

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Line Edge Roughness Reduction Using Resist Reflow Process for 22 nm Node Extreme Ultraviolet Lithography

Cho

Kim

You

et al. 2010

Jpn. J. Appl. Phys.

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Extreme ultraviolet lithography (EUVL) has been developed and studied for a sub-22 nm semiconductor device. It is difficult to obtain a smooth sub-22 nm pattern because line edge roughness (LER) and linewidth roughness (LWR) cannot be controlled well. According to the 2008 ITRS roadmap, LER has to be below 1.3 nm to achieve a 22 nm node for EUVL. In our previous work, the resist reflow process (RRP), in which the resist is baked above the glass transition temperature (T g ), was very helpful for reducing LER and LWR for EUVL. LER and LWR could be decreased from 6 to 1 nm. As RRP time progresses, however, the critical dimension could become wider because the developed resist can flow more easily when the temperature is above T g . Therefore, another method is suggested to solve this problem. The developed resist, which is intentionally designed with a 1 : 3 line and space (L/S) (11 : 33 nm) pattern, is baked above T g . As a result, LER and LWR can be smoothed by RRP and we could achieve a 22 nm 1 : 1 L/S pattern with a small LER. #

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Section: Discussionmentioning

confidence: 98%

Section: Introductionmentioning

confidence: 99%

Line Edge Roughness Reduction Using Resist Reflow Process for 22 nm Node Extreme Ultraviolet Lithography

Cho

Kim

You

et al. 2010

Jpn. J. Appl. Phys.

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“…For a backend middle level inlaid trench or via pitch of 280nm [3] (as discussed in the previous section), a patterning choice can be made between the use of 248nm or 193nm lithography. 193nm lithography has the advantage of higher linearity and requires fewer enhancement techniques and/or less aggressive MBOPC.…”

Section: Cost Of Ownership (Coo)mentioning

confidence: 99%

Model-based design improvements for the 100-nm lithography generation

et al. 2002

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Due to the challenging design rule and CD control requirements of the lOOnm device generation, a large number of complex patterning techniques are likely to be used for random logic devices [ 1] . The complexity of these techniques places considerable strain upon model-based OPC software to identify and compensate for a wide range of printing non-idealities [2]. Additionally, the rapidly increasing cost of advanced reticles has increased the urgency of obtaining reticles devoid of process limiting design or OPC errors. We have evaluated the capability of leading edge model-based OPC software to meet the challenging lithography needs of the lOOnm device generation. Specifically, we have implemented and verified model usefulness to correct for pattern deformation in complex binary gate, contact and via processes utilizing highly optimized illumination. Additionally, we present results showing the abilities of model-based methods to accurately find design related printing problems in complementary phase shift gate designs before they are committed to an expensive reticle. ii. IntroductionCurrently in early 2002, leading semiconductor manufacturers are starting pilot-line production of test circuits for the lOOnm technology generation and actively planning development for the 7Onm technology generation. Both of these generations will be accomplished with high numerical aperture (NA) 193nm lithography as the main patterning strategy. The main lithographic challenges of these generations are the lack of linearity (low ki processes); the low depth of focus (DOF) which accompanies high-NA illumination use; the complexity of reticle erthancement technology (RET) or scanner illumination which improves DOF & linearity; and the extremely high cost of ownership (COO) for the leading edge tools necessary to handle these challenges. Other difficult challenges include the relative immaturity of 193nm photoresists, the rising cost (& cycletime) of sophisticated high-end reticles, and the need for complex postprocessing techniques to alter final etched CD values [1,2]. These are difficult problems to overcome before these technologies can be made into working and cost-effective manufacturing processes. The main strategy for overcoming or reducing these problems is the use of optical proximity correction (OPC) methods. The goal of this work is to evaluate the effectiveness of model-based OPC (MBOPC) methods for solving critical patterning problems of the lOOnm technology generation.

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100-nm generation contact patterning by low temperature 193-nm resist reflow process

Cited by 2 publications

References 0 publications

Line Edge Roughness Reduction Using Resist Reflow Process for 22 nm Node Extreme Ultraviolet Lithography

Line Edge Roughness Reduction Using Resist Reflow Process for 22 nm Node Extreme Ultraviolet Lithography

Model-based design improvements for the 100-nm lithography generation

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