Logic Threshold for Microring Resonator-Based BDD Circuits: Physical and Operational Analyses

Abstract

Moore's Law has been the fuel of expansive innovation in computing. The chip industry kept the Moore's law extant for almost four decades. However, the halt of the rapid progress of the silicon technology is incipient by reason of the physical limitations. Emerging computing proposals suggest several alternatives to current computing paradigms and technologybases. The photonic circuitry is one of the most promising candidates with its high operation speed, energy efficient passive components, low crosstalk and appropriateness for parallel computation. Among various approaches to photonic logic, microring resonator-based Binary-Decision Diagram (BDD) architectures have a special place due to their small circuit footprint. However, the physical limitations imposed on their logic implementation has not been studied in depth to enable design of efficient circuits. In this paper, we study the physical structure and operational details of a microring resonatorbased Half-Adder (HA) circuit and outline the conditions under which the performance and accuracy of information processing is compromised due to its physical characteristics. Our analyses significantly contribute to determining key physical features and operations concerning logic implementation of microring resonator based BDD HA, which informs the future design and operational optimization of the microring resonator-based BDD logic circuits.

Physical Limitations on Fundamental Efficiency of SET-Based Brownian Circuits

“…There is an ongoing effort to assess the fundamental limitations of novel circuit paradigms, to help assess upcoming trends in the future of computing [ 12 , 13 , 14 , 15 , 16 , 17 , 18 , 19 , 20 , 21 , 22 , 23 , 24 , 25 , 26 ]. Recent experiments show that we can obtain energy dissipation in the -level [ 27 ].…”

“…The fundamental lower bounds of a given technology-base allow us to obtain best-case scenarios of performance projections based on the underlying computing strategy by taking the inefficiencies that are imposed by the nature of computing paradigms into account. In our earlier work, we laid out the foundations of a methodology to obtain fundamental efficiency limits for complex computing structures and calculated the fundamental lower bounds on energy dissipation at the circuit level for non-transistor-based [ 15 , 16 ], transistor-based nanoelectronic technology proposals [ 17 ], and optical microring resonator-based logic circuits [ 24 , 25 ], as well as at the nanoprocessor level [ 18 , 26 ]. The approach has also been implemented in finite-state machines [ 19 ].…”