10-Gb/s 850-nm CMOS OEIC Receiver With a Silicon Avalanche Photodetector

Youn, Jong-Chan; Lee, Myoung-Jae; Park, Kang-Yeob; Choi, Woo-Young

doi:10.1109/jqe.2011.2170405

Cited by 67 publications

(42 citation statements)

References 19 publications

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“…The measured transimpedance gain and 3-dB bandwidth is 86 dBΩ and 12 GHz, respectively. The sensitivity of our optical receiver circuit for BER less than 10 -12 can be estimated using the following equation [10] , 14.1 ( 1) 10 log 1000 2 ( 1) n Rx e e I r Sensitivity r…”

Section: Post Amplifiermentioning

confidence: 99%

“…Although monolithically integrated optical receivers that contain both photodetectors (PDs) and electronic circuits are highly desirable [1], most integrated optical receivers for highspeed applications are based on III-V semiconductors which may have disadvantages in cost consideration. A hybrid approach in which photodetectors and receiver circuits are implemented in different technologies and electrically connected on a board is routinely used.…”

Section: Introductionmentioning

confidence: 99%

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Design Optimization of Hybrid-Integrated 20-Gb/s Optical Receivers

Jung¹,

Youn²,

Choi³

2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-This paper presents a 20-Gb/s optical receiver circuit fabricated with standard 65-nm CMOS technology. Our receiver circuits are designed with consideration for parasitic inductance and capacitance due to bonding wires connecting the photodetector and the circuit realized separately. Such parasitic inductance and capacitance usually disturb the high-speed performance but, with careful circuit design, we achieve optimized wide and flat response. The receiver circuit is composed of a transimpedance amplifier (TIA) with a DC-balancing buffer, a post amplifier (PA), and an output buffer. The TIA is designed in the shunt-feedback configuration with inductive peaking. The PA is composed of a 6-stage differential amplifier having interleaved active feedback. The receiver circuit is mounted on a FR4 PCB and wire-bonded to an equivalent circuit that emulates a photodetector. The measured transimpedance gain and 3-dB bandwidth of our optical receiver circuit is 84 dBΩ and 12 GHz, respectively. 20-Gb/s 2 31 −1 electrical pseudo-random bit sequence data are successfully received with the bit-error rate less than 10 −12. The receiver circuit has chip area of 0.5 mm × 0.44 mm and it consumes excluding the output buffer 84 mW with 1.2-V supply voltage.

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Section: Post Amplifiermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Design Optimization of Hybrid-Integrated 20-Gb/s Optical Receivers

Jung¹,

Youn²,

Choi³

2014

JSTS:Journal of Semiconductor Technology and Science

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“…The dummy APD delivers symmetric impedance to the differential TIA input. An offset cancellation network composed of low-pass filters and a f T -doubler amplifier is added after the TIA in order to convert pseudo-differential TIA output into fully differential [10]. Its low cut-off frequency is set to 1 MHz in order to prevent any DC wander.…”

Section: Silicon Photonics-wireless Interfacementioning

confidence: 99%

Silicon Photonics-Wireless Interface IC for 60-GHz Wireless Link

Youn

Lee

et al. 2012

IEEE Photon. Technol. Lett.

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Abstract-We demonstrated a silicon photonics-wireless interface integrated circuit (IC) realized in 0.25-µm SiGe bipolar complementary metal-oxide-semiconductor technology, which converts 850-nm optical nonreturn-to-zero data into 60-GHz binary phase-shift keying wireless data. A transmission of 1.6 Gb/s in 60 GHz using the interface IC is successfully demonstrated with the error-free operation achieved at 6-dBm optical input power.

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“…In these applications, short wavelength vertical-cavity surface-emitting lasers (VCSELs) and silicon (Si) photodiodes (PDs) are used for low-cost system configuration. Si PDs fabricated by CMOS process are promising optical devices for easy integration with electronic circuits without any process modification [4][5][6], and avalanche photodiodes fabricated by CMOS process (CMOS-APDs) have been developed for optical interconnection applications [7][8][9][10]. The bandwidth of the CMOS-APD, however, is limited by slow photo-generated carriers from the substrate because all the electrodes are arranged on the surface of the substrate.…”

Section: Introductionmentioning

confidence: 99%

Characterizing Silicon Avalanche Photodiode Fabricated by Standard 0.18µm CMOS Process for High-Speed Operation

Napiah

Gyobu

Hishiki

et al. 2016

IEICE Trans. Electron.

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SUMMARYnMOS-type and pMOS-type silicon avalanche photodiodes (APDs) were fabricated by standard 0.18 µm CMOS process, and the current-voltage characteristic and the frequency response of the APDs with and without guard ring structure were measured. The role of the guard ring is cancellation of photo-generated carriers in a deep layer and a substrate. The bandwidth of the APD is enhanced with the guard ring structure at a sacrifice of the responsivity. Based on comparison of nMOS-type and pMOS-type APDs, the nMOS-type APD is more suitable for high-speed operation. The bandwidth is enhanced with decreasing the spacing of interdigital electrodes due to decreased carrier transit time and with decreasing the detection area and the PAD size for RF probing due to decreased device capacitance. The maximum bandwidth was achieved with the avalanche gain of about 10. Finally, we fabricated a nMOS-type APD with the electrode spacing of 0.84 µm, the detection area of 10 × 10 µm 2 , the PAD size for RF probing of 30 × 30 µm 2 , and with the guard ring structure. The maximum bandwidth of 8.4 GHz was achieved along with the gain-bandwidth product of 280 GHz.

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10-Gb/s 850-nm CMOS OEIC Receiver With a Silicon Avalanche Photodetector

Cited by 67 publications

References 19 publications

Design Optimization of Hybrid-Integrated 20-Gb/s Optical Receivers

Design Optimization of Hybrid-Integrated 20-Gb/s Optical Receivers

Silicon Photonics-Wireless Interface IC for 60-GHz Wireless Link

Characterizing Silicon Avalanche Photodiode Fabricated by Standard 0.18µm CMOS Process for High-Speed Operation

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