10:4 MUX and 4:10 DEMUX gearbox LSI for 100-gigabit Ethernet link

Ono,; Watanabe, Toru; Muto,; Yamashita,; Fukuda,; Masuda,; Nemoto,; Сузуки,; Takemoto,; Yuki,; Yagyu,; Toyoda,; Kambe,; Saito,; Nishimura,

doi:10.1109/isscc.2011.5746258

Cited by 14 publications

(8 citation statements)

References 1 publication

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Nevertheless, such timing scheme can greatly reduce the hardware cost. Compared with the conventional transmitter in [2][3], the proposed architecture only use seven D flip-flops in the data shifter and the data retimer. Without any data rate downgrade, the proposed architecture becomes hardware efficient.…”

Section: Proposed Transmitter Structurementioning

confidence: 99%

See 1 more Smart Citation

A 2×25Gb/s 20mW serializing transmitter with 2.5:1 multiplexers in 40nm technology

Lin

Chang

Lee

2016

2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

View full text Add to dashboard Cite

A low-power serializing transmitter is proposed by using a 2.5:1 multiplexer. Owing to its fractional multiplexing operation, only a single clock is needed to simplify the clock generator design as well as hardware cost. Fabricated in a 40 nm CMOS technology, the transmitter can generate 2-channel 25-Gbps signals. The transmitter consumes only 24 mW from a 0.9-V power supply. Keywords-serializing transmitter; fractional multiplexer; 100GbE transmitter.I.978-1-4673-9498-7/16/$31.00 ©2016 IEEE

show abstract

Section: Proposed Transmitter Structurementioning

confidence: 99%

“…In 100GbE architecture [2][3], ten 10-Gb/s channels need to be combined to four 25-Gb/s channels. In order to implement such 10 to 4 non-integer multiplexing, de-multiplexers are required to downconvert 10-Gb/s data to lower speed first and then multiplexers are used to upconvert to 25-Gb/s data.…”

Section: Introductionmentioning

confidence: 99%

A 2×25Gb/s 20mW serializing transmitter with 2.5:1 multiplexers in 40nm technology

Lin

Chang

Lee

2016

2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

View full text Add to dashboard Cite

show abstract

“…Now correlating PD3 from (19) with the PD1 output given by (11) and making the same assumptions about jitter being uncorrelated gives (20)…”

Section: Analysis Of Clock Jitter Measurementmentioning

confidence: 99%

“…The PD uses sense-amp based latches due to their narrower sampling aperture [18]. Double-tail latches based on those used in [19] and shown in Fig. 11 are used.…”

Section: B Cdr Implementationmentioning

confidence: 99%

On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs

Liang

Jalali

Sheikholeslami

et al. 2015

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

On-chip jitter measurement can be used to optimize the performance of wireline transceivers. In this work, the jitter of random data is measured on-chip by correlating the phase detector outputs from two adjacent CDR lanes. This allows the jitter's autocorrelation function to be estimated, from which the jitter's RMS value and power spectral density are extracted without using any external reference clock. The RMS value of random jitter ranging from 0.85 ps to 1.89 ps, and sinusoidal jitter from 0.89 ps to 5.1 ps is measured in PRBS31 data with less than 0.6 ps of error compared to measurements by an 80 GS/s real-time oscilloscope. Correlating the phase detectors in the CDRs with a third phase detector, which measures the phase difference between the clocks recovered by the two CDRs, allows measurement of the recovered clock jitter. Sinusoidal jitter from 1.8 ps to 5.3 ps is measured in the recovered clock with an error of less than 1 ps.Index Terms-Clock and data recovery, CDR, jitter, jitter measurement, on-chip measurement.

show abstract

“…Overall structure Figure 2 shows the entire block diagram of the developed 100-GbE gearbox LSI [2]. It consists of three blocks: a 10 × 10-Gb/s interface, a 4 × 25-Gb/s interface, and a MUX/ DEMUX block.…”

Section: Chip Designmentioning

confidence: 99%

A CMOS Low-Power 10:4 MUX and 4:10 DEMUX Gearbox IC for 100-Gigabit Ethernet Link

Fukuda

Ono

Watanabe

et al. 2011

2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)

Self Cite

View full text Add to dashboard Cite

show abstract

10:4 MUX and 4:10 DEMUX gearbox LSI for 100-gigabit Ethernet link

Cited by 14 publications

References 1 publication

A 2×25Gb/s 20mW serializing transmitter with 2.5:1 multiplexers in 40nm technology

A 2×25Gb/s 20mW serializing transmitter with 2.5:1 multiplexers in 40nm technology

On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs

A CMOS Low-Power 10:4 MUX and 4:10 DEMUX Gearbox IC for 100-Gigabit Ethernet Link

Contact Info

Product

Resources

About