1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS

Abstract

Abstruct-1-V power supply high-speed low-power digital circuit technology with 0.5-pm multithreshold-voltage CMOS (MTCMOS) is proposed. This technology features both lowthreshold voltage and high-threshold voltage MOSFET's in a single LSI. The low-threshold voltage MOSFET's enhance speed Performance at a low supply voltage of 1 V or less, while the high-threshold voltage MOSFET's suppress the stand-by leakage current during the sleep period. This technology has brought about logic gate characteristics of a 1.7-11s propagation delay time and 0.3-pW/MHz/gate power dissipation with a standard load. In addition, an MTCMOS standard cell library has been developed so that conventional CAD tools can be used to lay out low-voltage LSI's. To demonstrate MTCMOS's effectiveness, a PLL LSI based on standard cells was designed as a carrying vehicle. 18-MHz operation at 1 V was achieved using a 0.5-pm CMOS process.

Genetic Algorithm Based Fine-Grain Sleep Transistor Insertion Technique for Leakage Optimization

“…As shown in [12], the gate delay is influenced by the ST insertion. The load dependent delay d w/o (v) of gate v without ST is given by:…”

Sleep switch dual threshold Voltage domino logic with reduced standby leakage current

“…The leakage current of a cutoff high-transistor is orders of magnitude lower as compared to a low-transistor [5], [6]. Assuming a subthreshold slope of 85 mV/decade (a typical number in current CMOS technologies [15], [16]), an 85 mV increase in the threshold voltage of a transistor reduces the subthreshold leakage current by ten times.…”

dRail: A Novel Physical Layout Methodology for Power Gated Circuits

“…A number of solutions have been proposed for reducing the leakage power dissipation of digital circuits which include the use of dual-threshold logic [2], application of reverse body bias [3] and power gating [4]. Power gating is proven to be the most effective and practical technique for reducing leakage power when logic is idle.…”