This thesis investigates the effects of technology scaling on the flicker (or \lf) noise performance of deep submicron complementary metal-oxide-semiconductor (CMOS) transistors. Two major effects have been investigated, namely the employment of different gate dielectric growth and subsequent nitridation conditions, and the effects of geometry scaling. The first part of this work focus on the study of these two effects within the 0.25p.m technology node. Subsequently the scope of this study has been widened to examine the effects of scaling across a spectrum of technology nodes, namely 0.35um, 0.25um, 0.18pm and 0.13um. Finally the scope is further extended to cover the offering of different process flavours, as well as geometry scaling for the 0.13pm technology node. The 1//"noise performance of 0.25pm thin gate oxide transistors from the dual gate oxide thickness process and the single gate oxide thickness process have been evaluated and compared. A total of 20 transistors have been characterized. The results reveal that thin gate oxide transistors from the dual gate oxide thickness process show a maximum of an order reduction in the current noise spectra, as compared to their counterparts from the single gate oxide thickness process. This reduction can be attributed to the lower nitrogen concentration peak at the Si/SiC>2 interface. This lower nitrogen peak in turn correlates to a reduced oxide trap density at the interface, which has been verified via the chargepumping technique. Hence the dual gate oxide thickness process will be the state-of-theart for the implementation of low noise circuit designs. In general, the low frequency noise behaviour of the fabricated deep submicron metal-oxide-semiconductor field-effect transistors (MOSFETs) is best described by the correlated mobility fluctuation model.